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1 for more information www.linear.com/LTC4015 applications typical application features description multichemistry buck battery charger controller with digital telemetry system 12v in 2-cell li-ion 8a step-down battery charger controller step-down charger efficiency and coulomb counter error vs battery charge current l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and powerpath is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. n multichemistry li-ion/polymer, lifepo 4 , or lead- acid battery charger with termination n high efficiency synchronous buck battery charger n digital telemetry system monitors v b at , i b at , r b at ,ntc ratio (battery temperature), v in , i in , v system , die temperature n coulomb counter and integrated 14-bit adc n wide charging input voltage range: 4.5v to 35v n wide battery voltage range: up to 35v n input undervoltage charge current limit loop n maximum power point tracking n optional i 2 c serial port control n input current limit prioritizes system load output n input and output ideal diodes provide low loss powerpath? operation n instant-on operation with discharged battery n portable medical instruments/military equipment n industrial handhelds/lighting n ruggedized notebook/t ablet computers the lt c ? 4015 is a complete synchronous buck controller/ charger with pin-selectable, chemistry specific charging and termination algorithms. the LTC4015 can charge li- ion/ polymer, lifepo 4 , or lead- acid batteries. battery charge voltage is pin selectable and i 2 c adjustable. input current limit and charge current can be accurately programmed with sense resistors and can be individually adjusted via the i 2 c serial port. a digital telemetry system monitors all system power parameters. safety timer and current termination algorithms are sup - ported for lithium chemistry batteries. the LTC4015 also includes automatic recharge, precharge ( li-ion) and ntc thermistor protection. the LTC4015's i 2 c port allows user customization of charger algorithms, reading of charger status information, configuration of the maskable and programmable alerts, plus use and configuration of the coulomb counter. available in a 38-lead 5mm 7mm qfn package. charge current (a) efficiency (%) coulomb counter error (%) 4015 ta01b 100 90 95 80 85 70 75 60 55 65 50 0.5 0.0 ?0.5 ?1.0 ?1.5 ?2.0 0.1 10 1 efficiency qc error LTC4015 v in uvclfb controller v in 12v smbalert dv cc scl sda cells0 intv cc cells1 cells2 chem0 chem1 rt v c ccrefp ccrefm eq infet clp r snsi cln sys sysm5 4015 ta01a outfet sys intv cc drv cc boost tg sw bg cspm5 csp csn r ntcbias r snsb batsens ntcbias ntc lead-acid equalize charge (paddle) gnd sgnd 2p5v cc mppt r ntc 2-cell li-ion battery pack t ltc 4015 4015fb
2 for more information www.linear.com/LTC4015 table of contents features ............................................................................................................................ 1 applications ....................................................................................................................... 1 t ypical application ............................................................................................................... 1 description ......................................................................................................................... 1 absolute maximum ratings ..................................................................................................... 3 order information ................................................................................................................. 3 data sheet conventions ......................................................................................................... 3 pin configuration ................................................................................................................. 3 electrical characteristics ........................................................................................................ 4 t ypical performance characteristics ......................................................................................... 10 pin functions ..................................................................................................................... 13 block diagram .................................................................................................................... 15 i 2 c timing diagram ............................................................................................................. 16 operation..........................................................................................................................17 applications information ....................................................................................................... 42 register description ............................................................................................................ 49 det ailed register descriptions .............................................................................................. 55 t ypical applications ............................................................................................................. 72 package description ............................................................................................................ 74 revision history ................................................................................................................. 75 t ypical application .............................................................................................................. 76 related parts ..................................................................................................................... 76 ltc 4015 4015fb
3 for more information www.linear.com/LTC4015 pin configuration absolute maximum ratings (notes 1, 5) 13 14 15 16 top view 39 gnd uhf package 38-lead (5mm 7mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1cells1 cells2 dv cc scl sda smbalert sgnd uvclfb v c rt ntc ntcbias sys sysm5 outfet intv cc drv cc bg boost tg sw 2p5v cc mppt csp cells0 chem1 chem0 v in infet clp cln eq gnd cspm5 ccrefm ccrefp batsens csn 23 22 21 20 9 10 11 12 t jmax = 125c, ja = 34c/w (note 1) exposed pad ( pin 39) is gnd, must be soldered to pcb gnd order information lead free finish tape and reel part marking* package description temperature range LTC4015euhf#pbf LTC4015euhf#trpbf 4015 38-lead (5mm 7mm) plastic qfn C40c to 125c LTC4015iuhf#pbf LTC4015iuhf#trpbf 4015 38-lead (5mm 7mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. v in , csn ..................................................... C 0.3 v to 40 v boost to sw.............................................. C0.3 to 5.5 v batsens to csn , csp to csn , clp to cln , clp , cln to sys ................................................................ 0.3 v dv cc , drv cc ............................................. C0. 3 v to 5.5 v cellso , cells 1, cells 2, chem 0, chem 1, mppt , eq .......................................... C0. 3 v to intv cc sda , scl , smbalert .............................. C 0.3 v to dv cc i uvclfb ( note 4) .................................................. 200 a intv cc peak output current ................................ 10 0 ma operating junction temperature range ( n otes 2,3) ............................................. C 40 to 125 c storage temperature range ...................... C 65 to 150 c data sheet conventions ? v pinname and i pinname represents the voltage on a pin or the pin current; v eq = eq pin voltage. ? hexadecimal numbers are prefixed with 0x; 0 x10 is a hexadecimal 10 ? register symbol names will be capitalized. symbols within a register will be lower case; en_ meas _ sys_ valid_ alert is bit 15 in register en_limit_alerts (0x0d) ? lifepo 4 is lithium iron phosphate, li-ion is used for both lithium-ion and lithium-ion polymer ? lithium chemistries refers to lifepo 4 , lithium-ion, and lithium-ion polymer as a group. ? when a register name is used in square brackets, this means the 16 bit value associated with that register; for example [ vbat] is the 16 bit adc measurement value of the per cell battery voltage. http://www .linear.com/product/LTC4015#orderinfo ltc 4015 4015fb
4 for more information www.linear.com/LTC4015 electrical characteristics symbol parameter conditions min typ max units v in input supply voltage range note 8 l 3.1 35 v v bat battery voltage range note 8 l 35 v v charge(tol) charge voltage, regulated battery per cell tolerance, all chemistries li-ion ,4.2v per cell; lifepo 4 3.6v per cell; lead-acid 2.2v per cell l C1.25 1.25 % regulated battery charge current tolerance full-scale v cspCcsn /r snsb l C2.0 2.0 % v sys sys pin voltage note 8 l 3.05 35 v quiescent current i q = i vin + i clp + i cln + i sys + i sw + i csp + i csn + i batsens battery discharge current (no input supply, coulomb counter disabled) battery only, telemetry inactive l 112 325 a battery only, telemetry active 1% duty cycle l 140 364 a battery only, telemetry active continuously 2.84 ma i q , charging charging, switcher suspended 3.00 ma charging, v bat > v charge (note 7) 4.10 ma i q , ship mode ship mode (v in = 0) l 5 40 a i vin v in pin current battery only (no input supply) C200 200 na charging <140 a i sys sys pin current battery only, telemetry off 100 a battery only, telemetry on 2.75 ma charging, v bat > v charge ( note 7) 3.65 ma v in_duvlo v in to v batsens differential undervoltage (must be satisfied for charging) rising threshold hysteresis l 140 200 100 250 mv mv v in_ovlo input overvoltage lockout (inhibits charger) rising threshold hysteresis l 37.7 38.6 1.4 39.5 v v input under voltage current limit v uvclfb uvclfb pin regulation range (8-bit dac) v uvclfb maximum code 0xff v uvclfb minimum code 0x00 l 1188 1200 4.6875 1212 mv mv uvclfb pin regulation dac lsb 4.6875 mv uvclfb pin leakage current v uvclfb = 1.2v l C100 100 na input current limit regulated input current limit tolerance full-scale v clpCcln /r snsi l C2.0 2.0 % i cl input current limit range i cl = (v clp C cln )/r snsi 0.5 C 32 mv /r snsi input current limit lsb step size 0.5 mv /r snsi clp input current v clp = 12v, v clpCcln = 32mv 45 a cln input current v clp = 12v, v clpCcln = 32mv C100 100 na clp, cln common mode range note 8 4 35 v the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
5 for more information www.linear.com/LTC4015 symbol parameter conditions min typ max units intv cc regulator (sys is supply pin for this regulator) v intvcc internal regulator output voltage no load 5 v load regulation i intvcc = 50 ma 1.5 2.5 % v intvcc_cuvlo intv cc undervoltage charger lockout rising threshold hysteresis l 4.2 4.3 0.3 4.4 v v v intvcc_tuvlo intv cc undervoltage telemetry system lockout rising threshold hysteresis l 2.75 2.85 0.12 2.95 v v d rv cc input (external supply or supplied by intv cc ) v drvcc drv cc supply voltage 4.3 5.5 v drv cc undervoltage lockout rising threshold hysteresis l 4.1 4.2 0.3 4.3 v v battery charger (all chemistries) i charge battery charge current range, battery charge current resolution v csp > 2.6v (note 10) 1 C 32 1 mv /r snsb mv/r snsb peak low v csp charge current v csp < 2.4v 7.0 mv/r snsb i batsens + i csp + i csn charger suspended (telemetry active) v in , v sys = 12v, v batsens = 7.4v v in , v sys = 35v, v batsens = 34v (9 cells) 110 200 a a lithium-ion/lithium polymer battery charger lithium-ion/lithium polymer programmable, chem1, chem0 = [ll] (note 9) li-ion charge v oltage max dac setting code 11111 (note 11) 4.2 v/cell li-ion charge voltage min dac setting code 00000 (note 11) 3.8125 v/cell li-ion charge voltage dac lsb 12.5 mv li-ion recharge voltage percent of charge voltage 97.5 % charge c/x termination setting v cspCcsn (i 2 c termination option) 3.2 mv lithium-ion/lithium polymer fixed 4.2, 4.1, 4.0 charge v oltage, chem1, chem0 = [hh,lz,zl] (note 9) 4.2v fixed li-ion charge voltage chem1,0 = [h,h] (note 11) 4.200 v/cell 4.2v fixed li-ion recharge voltage chem1,0 = [h,h] 4.095 v/cell 4.1v fixed li-ion charge voltage chem1,0 = [l,z] (note 11) 4.100 v/cell 4.1v fixed li-ion recharge voltage chem1,0 = [l,z] 4.000 v/cell 4.0v fixed li-ion charge voltage chem1,0 = [z,l] (note 11) 4.000 v/cell 4.0v fixed li-ion recharge voltage chem1,0 = [z,l] 3.900 v/cell lithium-ion/lithium polymer, chem1, chem0 = [ll, hh, lz, zl] (note 9) low battery precharge threshold charge voltage = 4.2v 2.85 v/cell low battery precharge hysteresis charge voltage = 4.2v 50 mv/cell low battery precharge current i charge set to 32 mv/r snsb 3 mv/r snsb max charge time 18.2 hrs charge termination timer (default termination) 4 hrs electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
6 for more information www.linear.com/LTC4015 symbol parameter conditions min typ max units lifepo 4 battery charger lifepo 4 , programmable, chem1,chem0 = [lh] (note 9) lifepo 4 charge voltage max dac setting code 11111 (note 11) 3.8 v/cell lifepo 4 charge voltage min dac setting code 00000 (note 11) 3.4125 v/cell lifepo 4 charge voltage dac lsb 12.5 mv lifepo 4 recharge voltage por value i 2 c programmable 3.35 v/cell v lifepo 4 -c/x charge termination c/x threshold v csp-csn (i 2 c programmable) 3.2 mv lifepo 4 fixed standard charge, fixed fast charge, chem1, chem0 = [zh,hz] (note 9) lifepo 4 fixed fast charge absorb voltage chem1, chem0 = [hz] only (note 11) 3.8 v/cell lifepo 4 charge voltage chem1, chem0 = [zh,hz] (note 11) 3.6 v/cell lifepo 4 recharge voltage chem1, chem0 = [zh,hz] (note 11) 3.35 v/cell lifepo 4 , chem1, chem0 = [lh,hz,zh] (note 9) max charge time 18.2 hrs v lifepo 4 -t(cv) charge termination time 1 hrs lead-acid battery charger lead-acid fixed, chem1, chem0 = [zz] (note 9) v lead_acid_vcharge lead-acid v charge , equalization lead-acid v charge , absorption lead-acid v charge , cv lead-acid temperature compensation ( note 11) (note 11) (note 11) 2.6 2.4 2.2 C3.65 v/cell v/cell v/cell mv / cell/c lead-acid programmable, chem1, chem0 = [hl] (note 9) v lead_acid_vcharge lead-acid v charge dac maximum lead-acid v charge dac minimum lead-acid v charge dac resolution lead-acid temperature comp code 111111 (note 11) code 000000 (note 11) t emperature comp enabled 2.6 2.0 9.5 C3.65 v/cell v/cell mv mv/cell/c thermistor (ntc) bias v ntcbias applied ntc bias voltage internally switched to 1.2v 1.2 v i ntc ntc leakage current C50 50 na sysm5, cspm5 regulators C5v vinm5 v sys C v sysm5 , v csp C v cspm5 no load 4.8 v power path/ideal diode controllers v fto forward turn-on voltage 50 mv v fr forward regulation 15 mv v rto reverse turn-off C30 mv t if(on) infet turn-on time infet C v in > 3v, c infet = 3.3nf 550 s t if(off) infet turn-off time infet C v in < 1v, c infet = 3.3nf 2 s t of(on) outfet turn-on time vbat C outfet > 3v, c outfet = 3.3nf 2.3 s t of(off) outfet turn-off time vbat C outfet < 1v, c outfet = 3.3nf 1.9 s inductor current regulation i lim cycle by cycle max charge current note 5 l 47 52 57 mv/r snsb i rev reverse inductor current l 3.8 7.0 10 mv/r snsb electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
7 for more information www.linear.com/LTC4015 symbol parameter conditions min typ max units oscillator f osc switching frequency r t = 95.3k l 475 500 525 khz f max maximum programmable frequency r t = 47.5k 1 mhz f min minimum programmable frequency r t = 237k 200 khz gate drivers r up-tg tg pull-up on-resistance 2.0 r down-tg tg pull-down on-resistance 0.5 r up-bg bg pull-up on-resistance 2.0 r down-bg tg pull-down on-resistance 0.5 t r-tg tg 10% to 90% rise time c load = 3.3nf 20 ns t f-tg tg 90% to 10% fall time c load = 3.3nf 10 ns t r-bg bg 10% to 90% rise time c load = 3.3nf 20 ns t f-bg bg 90% to 10% fall time c load = 3.3nf 10 ns t no non-overlap time 60 ns t on(min) minimum on-time 140 ns dc max maximum duty cycle 98.4 % vc error amplifier g m transconductance to v c pin g m (v cspCcsm ) (constant-current) g m (v batsens ) (constant-voltage lithium) g m (v batsens ) (constant-voltage la) g m (v uvclfb ) (input voltage regulation) g m (v clpCclm ) (input current limiting) 2 cell; (gm = 1.06 C3 ? 2/(7 ? cell count) 6 cell; (gm = 1.06 C3 ? 3/(7 ? cell count) 4.10 0.15 0.08 1.06 4.10 mmho mmho mmho mmho mmho telemetry a/d measurement subsystem, battery only mode v err measurement error (note 6) v in = 1v v in = 35v 100 1.5 mv % v sys = 2.5v v sys = 35v 100 1.5 mv % v bat = 1.75v, 1 cell li-ion v bat = 35v, 9 cell li-ion 50 1.5 mv % v clpCcln = 0mv v clpCcln = 32mv 200 2.5 v % v cspCcsn = 0mv v cspCcsn = 32mv 200 2.5 v % ntc/ntcbias = 50%, 75% ntc/ntcbias = 5% 2 3.5 % % electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
8 for more information www.linear.com/LTC4015 symbol parameter conditions min typ max units coulomb counter v sense sense voltage differential input range v cspCcsn 50 mv q lsb charge measurement resolution prescaler m = 512 (default) 0.017 mvhr tce total charge error 10mv |v sense | 50mv 1.5 % 10mv |v sense | 50mv l 2.5 % v sense = 1mv <1.0 % i qc_csp i q C coulomb counter v sense = 30mv, battery only 78 a cells0, cells1, cells2, chem0, chem1 programming input pins (note 9) v ihpp input high threshold int vcc C v pin l 0.3 v v ilpp input low threshold v pin l 0.3 v r izpp input high-z test resistance internal 50k/50k resistor divider applied to inputs during chemistry/cell read 25 k mppt, eq input pins mppt, eq input high threshold l 1.1 v mppt, eq input low threshold l 0.2 v mppt, eq pin leakage current v eq , v mppt = 5v 0 1 a smbalert pin characteristics i smbalert smbalert pin leakage current v smbalert = 5v 0 1 a v smbalert smbalert pin output low voltage i smbalert = 1ma 65 100 mv i 2 c port, sda, scl dv cc i 2 c logic reference level 1.6 5.5 v i dvccq dv cc current scl/sda = 0khz 0 a address i 2 c address 1101_000[r/w]b v ihi2c input high threshold 70 % dv cc v ili2c input low threshold 30 % dv cc i ihi2c input leakage high C1 1 a i ili2c input leakage low C1 1 a v oli2c digital output low (sda) i sda = 3ma 0.4 v f scl scl clock frequency 400 khz t low low period of scl clock 1.3 s t high high period of scl clock 0.6 s t buf bus free time between start and stop conditions 1.3 s t hd( sta ) hold time, after (repeated) start condition 0.6 s t su( sta ) setup time after a repeated start condition 0.6 s t su(sto) stop condition set-up time 0.6 s electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
9 for more information www.linear.com/LTC4015 symbol parameter conditions min typ max units t hd( dat (out)) output data hold time 0 900 ns t hd) dat (in)) input data hold time 0 ns t su( dat ) data set-up time 100 ns t sp input spike suppression pulse width 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC4015 is tested under pulsed load conditions such that t j t a . the LTC4015e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC4015i is guaranteed over the C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (pd, in watts) according to the formula: t j = t a + (pd ? ja ) where ja = 34c/w for the uhf package. note 3: the LTC4015 includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: uvclfb is internally clamped above the maximum uvclfb regulation point (2.5v at 200a nominally). maximum input current must be limited to 200a when this clamp is reached. note 5: the current limit features of this part are intended to protect the ic from short term or intermittent fault conditions. continuous operation above the maximum specified pin current may result in device degradation or failure. note 6: measurement error is the magnitude of the difference between the actual measured value and the ideal value. error for v clp-cln and v csp-csn is expressed in v, a conversion to an equivalent current may be made by dividing by the sense resistors, r snsi and r snsb , respectively. note 7: v charge is the battery charge voltage (or cv, constant-voltage) target. v bat is the battery voltage. dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see the applications information section. note 8: v in , or v bat for battery only operation, may be connected to any suitable dc power source from 2.8v to 35v such that the voltage at v sys is high enough to allow intv cc to support the desired mode of operation. in order for the telemetry system to operate, intv cc must exceed the telemetry undervoltage lockout (v intvcc_tuvlo ). in order for the battery charger to operate, intv cc must exceed the charger undervoltage lockout (v intvcc_cuvlo ). allowing for 0.3v of drop from v in to intv cc , these modes require a minimum input voltage of 3.1v and 4.35v, respectively. additionally the v in to v batsens (v in_dulvo ) differential must also be satisfied for charging. note 9: chemistry selection is made using the chem1 and chem0 pins. these are three-state pins used by the LTC4015 to select of one of nine chemistry specific charging algorithms. these pins should be hard wired to gnd(l), intv cc (h), or left open (z > 1000k). note 10: i charge is the battery charge current (or cc, constant-current) target. i chg is the charge current when charging. note 11: charge voltage tolerance is v charge(tol) which is specified at the beginning of the electrical table. the LTC4015 is not a substitute for pack protection! the 4015 does not monitor or balance individual cells C the full stack voltage is divided by number of cells for simplicity only. electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. (note 2), dv cc = 3.3v, uvclfb = 1.5; cells1 = intv cc ; eq, mppt, cells0, cells2, chem0, chem 1 = 0; rt = 95.3k ; r ccref = 301k , r ntcbias = r ntc = 10k ; batsens = csn = csp; drv cc = intv cc ; sys = clp = cln. conditions: charging; v in = 12v , sys = 12v , batsens = 7.4v ..battery only; v in = 0v , sys = 8.4v , batsens = 8.4v ltc 4015 4015fb
10 for more information www.linear.com/LTC4015 typical performance characteristics v in (resistive), mppt enabled charger on/off li-ion charging efficiency vs v in lead-acid charging efficiency vs i charge lifepo 4 charging efficiency vs i charge charge voltage (cv mode) vs junction temperature v rsnsb current (cc mode) vs junction temperature lead-acid charging profile voltage, current vs time li-ion charging profile voltage, current vs time lifepo 4 charging profile voltage, current vs time t a = 25c, application circuit 1 unless otherwise noted. ltc 4015 4015fb 11.5 charge voltage charge current v charge = 3.6v/cell cellcount = 4 v in , charger off (v) 10 15 20 25 30 35 12.0 0 5 10 15 20 25 30 v in charger on (v) 4015 g04 v in , mppt enabled 12.5 v in /2, charger off v bat + 1v v in resistance 4.5 v charge = 4.2v/cell v bat held at 6.6v v in (v) 10 15 20 25 30 13.0 80 82 84 86 88 90 92 94 96 efficiency (%) 13.5 4015 g05 i charge = 0.75a i charge = 4a i charge = 8a v bat held at 7.4v cellcount = 2 i charge (a) 0 1 2 3 14.0 4 5 6 8 7 70 75 80 85 90 14.5 95 100 efficiency (%) 4015 g06 i charge v in = 24v v bat held at 12.2v cellcount = 6 i charge (a) 0 1 2 15.0 3 4 5 6 7 8 84 86 88 90 0 92 94 96 98 efficiency (%) 4015 g07 i charge v in = 30v v bat held at 23.5v cellcount = 7 junction temperature (c) ?50 0.5 ?30 ?10 10 30 50 70 90 110 130 8.370 time (minutes) 1.0 8.375 8.380 8.385 8.390 8.395 8.400 8.405 charge voltage (v) 4015 g08 i charge = 0 1.5 i charge = 100ma li-ion 4.2v/cell charge voltage v in = 12v cellcount = 2 junction temperature (c) ?50 ?30 ?10 10 30 50 70 2.0 90 110 130 31.86 31.88 31.90 31.92 31.94 31.96 31.98 2.5 32.00 32.02 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0.00 3.0 0.25 v rsnsb (v) v rsnsb error (%) 4015 g09 li-ion 4.2v/cell charge voltage v in = 12.v, v bat = 8v cellcount = 2 full-scale v rsnsb error from 25c 3.5 battery voltage (v) battery current (a) 4015 g01 charge voltage 0 charge current v absorb = 2.4v/cell v charge = 2.2v/cell cellcount = 6 r snsi = 0.007 r snsb = 0.010 time (minutes) 0 15 30 45 60 75 50 90 105 120 135 7.2 7.4 7.6 7.8 8.0 8.2 100 8.4 8.6 0 1 2 3 4 5 6 7 150 8 battery voltage (v) battery current (a) 4015 g02 charge voltage charge current v charge = 4.2v/cell cellcount = 2 time (minutes) 0 200 15 30 45 60 75 90 105 120 135 11.0 250 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 0 1 11.0 2 3 4 5 6 7 8 battery voltage (v) battery current (a) 4015 g03
11 for more information www.linear.com/LTC4015 typical performance characteristics rt oscillator frequency vs junction temperature battery discharge current vs battery voltage battery charger soft-start (i charge vs time) gate drive non-overlap (transient) v in hot plug, 0 to 24v, 4-cell lifepo 4 battery hot plug, 0 to 11v, 4-cell lifepo 4 v rsnsi charging (icl mode) vs junction temperature uvclfb voltage (uvcl mode) vs junction temperature input current limiting i in and i charge vs system load t a = 25c, application circuit 1 unless otherwise noted. ltc 4015 4015fb 90 battery voltage (v) 0 5 10 15 20 25 30 35 0 110 50 100 150 200 250 300 battery discharge current (a) 4015 g14 t = ?45c t = 25c 130 t = 60c t = 125c v in = 0 coulomb counter off i charge max = 8a r snsb = 0.004 2ms/div 4015 g15 i charge 2a/div v in = 12v v bat = 7.4v v sw 2v/div 200ns/div 1.1965 4015 g16 tg, bg non overlap 4015 g17 iin vin vbat iin 20a/div ibat 20a/div vin 5v/div vbat 5v/div 1.1971 500s/div ibat = green 4015 g18 ibat ibat 20a/div vbat 5v/div vsys 5v/div vbat = blue vsys = red 200s/div 1.1976 1.1982 1.1988 1.1994 1.1999 junction temperature (c) 1.2005 charge voltage (v) 4015 g11 uvclfb, full-scale li-ion 4.2v/cell v charge v in = 12v, v bat = 7.4v v in resistance 2 cellcount = 2 system load (a) 0 2 4 6 ?50 8 10 12 0 4 8 12 16 20 amps ?30 4015 g12 i in , v in = 12v i charge , v in = 12v i in , v in = 24v i charge , v in = 24v i in , v in = 35v i charge , v in = 35v junction temperature (c) ?50 ?30 ?10 10 30 50 70 ?10 90 110 130 495 496 497 498 499 500 501 10 502 503 frequency (hz) 4015 g13 r t = 95.3k junction temperature (c) ?50 ?30 ?10 10 30 30 50 70 90 110 130 31.86 31.88 31.90 31.92 50 31.94 31.96 31.98 32.00 32.02 ?1.75 ?1.00 ?1.25 ?1.50 ?0.75 70 ?0.50 ?0.25 0.00 0.25 v rsnsb (v) v rsnsi error (%) 4015 g10 v rsnsi error from 25c li-ion 4.2v/cell v charge v in = 12v, v bat = 7.4v system load = 7a cellcount = 2
12 for more information www.linear.com/LTC4015 typical performance characteristics coulomb counter accuracy vs v cspCcsn start-up from 24v v in hot plug, i charge = 8a (r snsb = 0.004) ship mode battery discharge current vs battery voltage mppt algorithm using uvcl dac sweep to find mpp v csp ? v csn (mv) error (%) 4015 g24 0.5% 0.0% ?0.5% ?1.0% ?1.5% ?2.0% ?2.5% 3.0% 3.5% 0 15 20 25 30 35 105 qc error ltc 4015 4015fb 35 0 5 10 15 20 25 30 35 battery discharge current (a) battery voltage (v) 4015 g20 t = 125c t = 60c t = 25c t = ?45c v in source impedance = 4.4 4015 g21 maximum i charge found during uvcl dac sweep v bat v in , at max i charge found during uvcl dac sweep v in , no load = 25v uvcl dac sweep vin 5v/div 0 vbat 5v/div i charge 2a/div 400ms/div 4015 g19 i bat iin v bat vin v in 5v/div v bat 5v/div 5 i in 5a/div i bat 5a/div 200s/div 10 15 20 25 30
13 for more information www.linear.com/LTC4015 pin functions cells1 (pin 1): number of cells select pin. three-state pin used in combination with cells0 and cells2 to set the total number of battery cells. cells2 (pin 2): number of cells select pin. three-state pin used in combination with cells0 and cells1 to set the total number of battery cells. dv cc (pin 3): logic supply for the i 2 c serial port. dv cc sets the reference level of the sda and scl pins for i 2 c compliance. it must be connected to the same power supply used to power the i 2 c pull up resistors. if the i 2 c port is unused connect this pin to intv cc , do not float. scl (pin 4): clock input for the i 2 c serial port. the i 2 c input levels are scaled with respect to dv cc for i 2 c compliance. if the i 2 c port is unused connect this pin to intv cc , do not float. sda (pin 5): data input/output for the i 2 c serial port. the i 2 c input levels are scaled with respect to dv cc for i 2 c compliance. if the i 2 c port is unused connect this pin to intv cc , do not float. smbalert (pin 6): open-drain interrupt request. pulls low when something important needs to be reported back to the system. sgnd ( pin 7): signal ground. all small signal components and compensation should connect to this ground, which should be connected to pgnd at a single point. uvclfb (pin 8): undervoltage current limit feedback pin. uvclfb can be used to reduce charge current when the v in pin reaches a level programmed by the user sup- plied resistor divider. this feature can be used for power sources with higher source impedance such as a solar panel. maximum charge current is tapered off when this pin is below 1.2 v, at 1.15 v the charge current is zero. uvclfb is internally clamped to about 2.5 v with 200a in this pin. limit the current into this pin to 200 a at maximum v in using the thevenin resistance of the input divider. if the input undervoltage current limit feature is not desired, connect uvclfb to 2p5v cc through a 10k resistor or to v in through an appropriately sized resistor. vc (pin 9): current control threshold and error amplifier compensation point. the current comparator threshold increases with this control voltage. the voltage normally ranges from 900mv to 2.4v. rt ( pin 10): connect a resistor from rt to gnd to set frequency of the switching power supply. ntc (pin 11): thermistor input. the ntc pin connects to a negative temperature coefficient thermistor (type_2) to monitor the temperature of the battery. the voltage on this pin is digitized by the analog to digital converter and is available via the i 2 c port. the thermistor value is also used to qualify battery charging. connect a low drift bias resistor from ntcbias to ntc and a thermistor from ntc to ground. if ntc functions are unwanted, use a resistor equal in value to r ntcbias instead of a thermistor. ntcbias (pin 12): ntc thermistor bias output. connect a bias resistor between ntcbias and ntc, and a thermis- tor between ntc and gnd. the bias resistor should be equal in value to the nominal value of the thermistor. the LTC4015 applies 1.2 v to this pin during ntc measurement. eq (pin 13): equalize. apply a logic signal between 1.5v and intv cc (5 v) to this pin to allow the 4015 to trigger lead-acid equalize mode. gnd this pin if unused, do not float. gnd (pin 14, exposed pad pin 39): ground. the exposed pad should be connected by multiple vias directly under the LTC4015 to a continuous ground plane on the second layer of the printed cir cuit board. cspm5 (pin 15): internal supply pin. the v cspm5 pin regulates at the higher of ground or approximately v csp C 5 v. a low impedance multilayer ceramic capacitor should be connected from v csp to v cspm5 . ccrefm (pin 16): coulomb counter reference resis- tor pin. leakage on this pin will affect coulomb counter accuracy. connect a 301k, 0.1%, 25 ppm resistor from ccrefm to ccrep. ccrefp (pin 17): coulomb counter reference resis- tor pin. ccrefp in conjunction with ccrefm provide a reference for the coulomb counter to make an accurate measure of charge into and out of the battery. ccrefp is connected internally to csp with 50. connect a 301k, 0.1%, 25ppm resistor from ccrefp to ccrem. ltc 4015 4015fb
14 for more information www.linear.com/LTC4015 pin functions batsens (pin 18): battery voltage sense input. for proper operation, this pin must be connected physically close to the positive input terminal of the battery. csn (pin 19): connection point for the negative terminal of the charge current sense resistor. csp (pin 20): connection point for the positive terminal of the charge current sense resistor. mppt (pin 21): mppt enable pin. apply a logic signal between 1.5 v and intv cc (5 v) to this pin to allow the 4015 to enter mppt mode. mppt mode can also be entered via the i 2 c port. gnd this pin if unused, do not float. 2p5v cc (pin 22): bypass pin for the internal 2.5 v regu- lator. this regulator provides power to the internal logic cir cuitry. bypass 2p5v cc with a 2.2 f multilayer ceramic capacitor to gnd. sw (pin 23): switch node. sw pin swings from a diode drop below ground up to v sys . tg (pin 24): top gate drive. drives the top n-channel mosfet with a voltage swing equal to drv cc superim- posed on the switch node voltage v sw . boost (pin 25): boosted floating top gate drive supply. the boost pin swings from a diode voltage below drv cc up to v sys + drv cc . bg ( pin 26): bottom gate drive. drives the bottom n-channel mosfet between drv cc and ground. drv cc (pin 27): external supply for gate driver. do not exceed 5.5 v on this pin. if drv cc is not connected to intv cc , intv cc must be greater than 3 v before drv cc is applied. if not connected to intv cc bypass this pin to ground with a low esr ceramic capacitor. intv cc (pin 28): internal 5 v regulator output. the control circuits and optionally the gate drivers are powered from this pin. bypass this pin to ground with a minimum 4.7f low esr tantalum or ceramic capacitor. outfet (pin 29): output ideal diode gate control pin for external p-channel mosfet. sysm5 (pin 30): internal supply pin. the v sysm5 pin regulates at the higher of ground or approximately v sys C 5 v. a low impedance multilayer ceramic capacitor should be connected from v sys to v sysm5 . sys (pin 31): system input voltage. primary power input to the 4015. this pin powers the internal intv cc ldo. sys is the max of v bat or v in . v sys should be bypassed with a low impedance multilayer ceramic capacitor, along with large bulk capacitors. cln (pin 32): connection point for the negative terminal of the input current sense resistor. clp ( pin 33): connection point for the positive terminal of the input current sense resistor. infet (pin 34): input ideal diode gate control pin for external n-channel mosfet. v in (pin 35): supply voltage for the powerpath step-down switching charger. v in may be connected to any suitable dc power source from 2.8 v to 35 v such that the voltage at v sys is high enough to allow intv cc to support the desired mode of operation. in order for the telemetry system to operate intv cc must exceed the telemetry undervoltage lockout. v in should be bypassed with a low impedance multilayer ceramic capacitor. chem0 (pin 36): chemistry select pin. three - state pin used in combination with chem1 to set the battery chemistry and charge algorithm. chem1 (pin 37): chemistry select pin. three - state pin used in combination with chem0 to set the battery chemistry and charge algorithm. cells0 (pin 38): number of cells select pin. three-state pin used in combination with cells1 and cells2 to set the total number of battery cells. ltc 4015 4015fb
15 for more information www.linear.com/LTC4015 block diagram clp 15mv d/a 6-bit 1.2v full-scale d/a 5b lithium chemistries 6b lead-acid 37.5 v in infet sysm5 sys outfet cln batsens uvclfb vc dv cc scl sda smbalert chem1 chem0 cells2 cells1 cells0 mppt eq +? ? + d/a 5-bit 1.2v full-scale ? + ? + ? + ? + ? + d/a 8-bit 1.2v full-scale rt logic 1.8v range, signed 16 bits lsb(1 count) = 3.6v/65535 = 54.9325v step-down switching controller i 2 c ?5v ldo coulomb counter oscillator ? + ccrefp csp cspm5 ccrefm csn boost tg sw drv cc bg v sys ntc gnd 4015 bd gnd gnd (paddle) gnd ?5v ldo a/d v batsens /[cellcount (7/2)] li chemistries v batsens /[cellcount (7/3)] lead-acid v in /30 v sys /30 i bat (37.5 (v csp ? v csn )) i in (37.5 (v clp ? v cln )) t_die intv cc 2p5v cc ntcbias 1.2v intv cc ldo 2.5v ldo 15mv +? 37.5 37.5 i in i bat ntc t_die v sys v in v bat 11 12 22 28 26 27 23 24 25 19 16 17 20 15 29 31 30 34 35 33 32 18 8 9 10 3 4 5 6 37 36 2 1 38 21 13 39 14 sgnd sgnd 7 ? + ltc 4015 4015fb
16 for more information www.linear.com/LTC4015 i 2 c timing diagram sda scl t hd(sta) t high t f t f t su(sto) t hd(dat) t low t su(sta) t hd(sta) t buf start condition stop condition repeated start condition start condition t su(dat) 4015 td t sp i 2 c smbus legend s start condition sr repeated start condition rd read (bit value of 1) wr write (bit value of 0) a acknowledge n nack p stop condition pec* packet error code master to slave slave to master smbus write word protocol s slave address wr a command code a data byte low a data byte high a p smbus write word with pec protocol s slave address wr a command code a data byte low a data byte high a pec* a p smbus read word protocol s slave address wr a command code a sr slave address rd a data byte low a data byte high n p smbus read word with pec protocol s slave address wr a command code a sr slave address rd a data byte low a data byte high a pec* n p smbus alert response address protocol s alert response address rd a device address rd n p smbus alert response address protocol with pec s alert response address rd a device address rd a pec* n p *use of packet error checking is optional ltc 4015 4015fb
17 for more information www.linear.com/LTC4015 operation introduction the LTC4015 is a li- ion/ lifepo 4 / lead- acid battery charger utilizing a step-down switching controller. it is designed to efficiently transfer power from a variety of possible sources, such as wall adapters and solar panels, to a battery and system load while minimizing power dissi - pation and easing thermal budgeting constraints. since a switching regulator conserves power, the LTC4015 allows the charge current to exceed the source's output current, making maximum use of the allowable power for battery charging without exceeding the source's delivery specifications. by incorporating input voltage and current measurement and control systems, the switching charger interfaces seamlessly to these sources without requiring application software to monitor and adjust system loads. by decoupling the system load from the battery and pri - oritizing power to the system, the instant- on powerpath architecture ensures that the system is powered immediately after v in is applied, even with a completely dead battery . tw o ideal diode controllers drive external mosfets to provide low loss power paths from v in and v bat to the system. tw o ideal diodes work with the charger to provide power from v bat to the system without back driving v in . the ideal diode from v bat to the system load guarantees that power is available to the system even if there is insuf - ficient or absent power from v in . the ideal diode from v in to the system load guarantees neither v bat or the system will back drive v in . a wide range of input current settings as well as battery charge current settings are available by software control and the values of sense resistors r snsi and r snsb . a measurement subsystem periodically monitors and re- ports system parameters via the i 2 c serial port. included in this subsystem is a coulomb counter to allow battery gas gauging. an interrupt subsystem can be enabled to alert the host microprocessor of various status change events so that system parameters can be varied as needed by the system. many status change events are maskable for maximum flexibility. to eliminate battery drain between manufacture and sale, a ship-and-store feature reduces the already low battery drain and optionally disconnects power from downstream circuitry. the input undervoltage current loop ( uvcl) can be engaged to help keep the input voltage from decreasing beyond a minimum voltage when a resistive cable or power limited supply such as a solar panel is providing input power to the LTC4015. a maximum power point algorithm using this control loop has been preprogrammed into the LTC4015 to maximize power extraction from solar panels and other resistive sources. finally, the LTC4015 has a digital subsystem that provides substantial adjustability so that power levels and status information can be controlled and monitored via the simple 2-wire i 2 c serial port. LTC4015 digital system overview the LTC4015 contains an advanced digital system which can be optionally accessed using the i 2 c serial port. the LTC4015 digital system can be used extensively in the application or not at all, as dictated by the application requirements. this data sheet provides extensive details of the digital functions of the LTC4015, though much of this detail is not required for simpler applications. use of the serial port is completely optional. even without use of the serial port, the LTC4015 is a fully functioning high performance battery charger which is highly configurable using external components and pin connections. chem - istry/algorithm, cell count, charge current, input current regulation ( icl), v in undervoltage regulation (uvcl), maximum power point tracking ( mppt), and switching charger frequency and compensation are all externally configurable without using the serial port. for applications requiring the LTC4015s advanced digital features, the serial port provides a means to use the cou - lomb counter , read status and adc telemetry data from the measurement system, monitor charger operation, configure charger settings ( e.g. charge voltage, charge current, temperature response, etc), enable/disable/read/ clear alerts, activate low power ship mode, and enable/ disable the battery charger. detailed information about the digital system and the serial port registers, as well as digital system usage examples, can be found in the section LTC4015 digital system. ltc 4015 4015fb
18 for more information www.linear.com/LTC4015 operation power path ideal diode controllers the LTC4015 features input and output ideal diode control - lers. these controllers make up a power path that allows power to be delivered to the system (v sys ) by either v in or v bat , whichever is greater. the input ideal diode provides a one way path from v in to v sys . the output ideal diode provides a one way path from v bat to v sys . the ideal diode controllers consist of a precision ampli- fier that drives the gate of a mos transistor whenever the voltage at v sys is approximately 15mv (v fwd ) below the voltage at v in or v bat . within the amplifiers linear range, the small signal resistance of the ideal diode will be quite low, keeping the forward drop near 15 mv. at higher cur - rent levels, the mos transistors will be in full conduction. the input ideal diode controller assumes control of an external nmos transistor by modulating the gate voltage of the nmos transistor to allow current to flow from v in to v sys while blocking current in the opposite direction to prevent back driving v in . additionally a fastoff comparator shuts off the nmos if v in falls 25mv below v sys . the output ideal diode provides a path for v bat to power v sys when v in is unavailable, while blocking current in the opposite direction to prevent overcharging of the battery. the output ideal diode controller controls an external pmos transistor by modulating the gate voltage of the pmos transistor. in addition to a fast-off comparator the output ideal diode also has a fast-on comparator that turns on the external mosfet when v sys drops 45 mv below v bat . when limited power is available to the switching charger because either the programmed input current limit or input undervoltage limit is active, charge current will automati - cally be reduced to prioritize power delivery to the system load. note that the LTC4015 only limits charge current, but does not limit current from the input to the system loadif the system load alone requires more power than is available from the input after charge current has been reduced to zero, v sys must fall to the battery voltage in order for the battery to provide supplemental power. note that a system load fault can dissipate very large amounts of power, as the system load current will not be limited by the ideal diode controllers. input current regulation (icl) the LTC4015 contains a control loop, icl ( input current limit), that automatically reduces charge current when the overall average input current reaches a maximum level. the input current regulation function can only reduce charge current to zero, it cannot limit the overall input current which is a function of the load on v sys . this level is set by the combination of the current sense resistor r snsi from clp to cln and either the default 32 mv servo voltage or a value programmed into iin_limit_setting via the serial port. the maximum servo voltage that can be programmed is 32 mv. the voltage across the sense resistor divided by its value determines the target maximum possible input current. a 2m resistor, for example, would have an upper limit of input current of 16a using a 32mv servo voltage. input undervoltage regulation (uvcl) and solar panel maximum power point tracking (mppt) the LTC4015 contains a control loop, uvcl ( under voltage current limit) that allows it to tolerate a resistive connection to the input power source by automatically reducing charge current as v in ( as observed at the uvclfb pin using a v in voltage divider ) drops to a programmable level ( vin_uvcl_setting). this circuit helps prevent uvlo oscillations by regulating the input voltage above the LTC4015s undervoltage lockout level. the uvcl function can only reduce charge current to zero, it cannot limit the overall input current which is also a function of the load on v sys . optionally, the LTC4015 includes a maximum power point tracking ( mppt) algorithm to find and track the vin_uvcl_setting that delivers the maximum charge current to the battery. if enabled by the mppt pin or by the mppt_en_i2c bit via the serial port, the mppt algorithm performs a sweep of vin_ uvcl_ setting values, measuring battery charge current at each setting. when the sweep is completed, the LTC4015 applies the vin_ uvcl_ setting value corresponding to the maximum battery charge current ( i.e. the maximum power point). the LTC4015 then tracks small changes in the maximum power point by slowly dithering the vin_uvcl_setting. the LTC4015 periodically performs a new sweep of ltc 4015 4015fb
19 for more information www.linear.com/LTC4015 operation vin_uvcl_setting values, applies the new maximum power point, and resumes dithering at that point. with the automatic mppt algorithm enabled, a solar panel can be used as a suitable power source for charging a battery and powering a load. the mppt feature can be enabled either via the serial port or by connecting the mppt pin to the 2p5v cc pin or a suitable gpio from a microcontroller. the mppt algorithm may not work for all solar panel applications and does not have to be used, alternatively a solar panel can be used without the mppt algorithm by setting the uvcl v in minimum value to match the optimum loaded solar panel voltage by selecting the appropriate vin_uvcl_setting and uvclfb pin resistor divider. serial port, smbus and i 2 c protocol compatibility the LTC4015 uses an smbus/i 2 c style 2- wire serial port for programming and monitoring functions. using the serial port, the user may program alerts, set control pa- rameters and read status data. the timing diagram shows the relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or active loads, such as the ltc1694 smbus accelerator, are required on these lines. the LTC4015 is both a slave receiver and slave transmitter. it is never a master. the control signals, sda and scl, are scaled internally to the dv cc supply in compliance with the i 2 c specification. dv cc must be connected to the same power supply as the bus pull-up resistors. aside from electrical levels and bus speed, the smbus specification is generally compatible with the i 2 c bus specification, but extends beyond i 2 c to define and stan- dardize specific protocol formats for various types of transactions. the LTC4015 serial port is compatible with the 400 khz speed and ratiometric input thresholds of the i 2 c specification and supports the read word and write word protocols of the smbus specification. it has built-in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input filters designed to suppress glitches. programmable alerts and interrupt controller the serial port supports the smbus smbalert proto - col. an alert can optionally be generated if a monitored parameter exceeds a programmed limit or if selected bat- tery charger states or status events occur. this offloads much of the continuous monitoring from the systems microcontroller and onto the LTC4015; reducing bus traffic and microprocessor load. the smbalert pin is asserted ( pulled low) whenever an enabled alert occurs ( see the following tables and register descriptions). the LTC4015 will de-assert ( release) the smbalert pin only after successfully responding to an smb alert response address ( ara). the alert response is an smb protocol used to respond to an smbalert . the host reads from the alert response address 0001_1001b (0x19) and each part asserting smbalert begins to respond with its address. the responding parts arbitrate in such a way that only the part with the lowest address responds. only when a part has responded with its address does it release the smbalert signal. if multiple parts are asserting the smbalert signal then multiple reads from the ara are needed. therefore, only a response of 1101_0001b (0 xd1) will clear the LTC4015/smbalert signal. any other response indicates a device with a lower i 2 c address also requests attention from the host. for more information refer to the smbus specification. table 1. shows a summary of LTC4015 limit alerts. each alert has an associated enable (mask), limit, and bit that is set to 1 to indicate the enabled alert has occurred. limit alerts alert enable bits (0x0d) alert limit set point register aler t reporting bits (0x36) measurement system v alid alert (adc ready) 15 n/a 15 reserved 14 n/a n/a coulomb counter accumulator low and high alert 13, 12 0x10, 0x11 13, 12 battery voltage low and high alert 11, 10 0x01, 0x02 11, 10 input voltage low and high alert 9, 8 0x03, 0x04 9, 8 system voltage low and high alert 7, 6 0x05, 0x06 7, 6 input current high alert 5 0x07 5 battery current low alert 4 0x08 4 die temperature high alert 3 0x09 3 battery series resistance high alert 2 0x0a 2 ntc ratio high and low alert 1, 0 0x0b, 0x0c 1, 0 ltc 4015 4015fb
20 for more information www.linear.com/LTC4015 operation table 2. shows a summary of LTC4015 charger state alerts. each alert has an associated enable (or mask), and bit that is set to 1 to indicate the alert has occurred. charger state alerts alert enable bits (0x0e) alert repor ting bits (0x37) equalize 10 10 absorb 9 9 charger suspended 8 8 precharge 7 7 cc_cv 6 6 ntc pause 5 5 t imer termination 4 4 c/x termination 3 3 max charge time fault 2 2 battery missing fault 1 1 battery short fault 0 0 table 3. shows a summary of LTC4015 charger status alerts. these alerts indicate which control loop is in control during charging. each alert has an associated enable ( or mask), and bit that is set to 1 to indicate the alert has occurred. charger status alerts alert enable bits (0x0f) alert reporting bits (0x38) uvcl (v in undervoltage charge current limiting) 3 3 icl (i in charge current limiting) 2 2 cc (constant-current mode) 1 1 cv (constant-voltage mode) 0 0 measurement subsystem the LTC4015 includes a 14- bit analog-to-digital converter (adc) and signal channel multiplexer to monitor several analog parameters. it can measure the voltages at v in , sys and batsens, the current into the sys node (voltage across r snsi ), the battery charge current ( voltage across r snsb ), the voltage across the battery pack thermistor, and its own internal die temperature. after a charge cycle begins the LTC4015 uses the appropriate analog parameters to calculate the series resistance of the battery. to save battery power the measurement system will not run if the battery is the only source of power, unless the force_meas_sys_on bit is set. the converter is automatically multiplexed between all of the measured channels and its results are stored in registers accessible via the i 2 c port. the seven channels measured by the adc each take ap- proximately 1.6ms to measure. the result of the analog- to -digital conversion is stored in a 16- bit register as a signed, twos complement number. the lower two bits of this number are sub-bits. these bits are adc outputs which are too noisy to be reliably used on any single conversion, however, they may be included if multiple samples are averaged. the maximum range of the adc is 1.8 v, which gives a lsb size of 3.6v/65535 (2 16 C 1). table 4 summarizes the lsb scaling and resultant lsb size for these adc measurements. table 4. measurement subsystem scaling and lsb size adc lsb (3.6v/65535) = 54.932479 v measurement register symbol register number lsb scaling lsb size units v batsens /cellcount (lithium chemistries) vbat 0x3a *7/2 192.264 v v batsens /cellcount (lead-acid) vbat 0x3a *7/3 128.176 v v in vin 0x3b *30 1.648 mv v sys vsys 0x3c *30 1.648 mv v rsnsb (v csp C v csn ) ibat 0x3d /37.5 1.465 v v rsnsi (v clp C v cln ) iin 0x3e /37.5 1.465 v die temperature (note 1) die_temp 0x3f 1 54.932 v note 1: die_temp is the adc conversion of a internal ptat (proportional to absolute temperature) voltage. die temperature = (die_temp C 12010)/45.6 in c. ltc 4015 4015fb
21 for more information www.linear.com/LTC4015 figure 1. ntc bias configuration 4015 f01 r ntcbias ntcbias ntc t r ntc thermistor operation when input power is absent, the measurement system can be sampled periodically at reduced battery load using the following procedure as an example: a. write en_meas_sys_valid_alert = 1 b. write force_meas_sys_on = 1 c. wait for smbalert to go low (typically 20 ms from force_meas_sys_on = 1) d. upon smbaler t going low, perform ara command. if there are multiple slave devices, verify that the LTC4015 is asserting the alert. e. verify meas_sys_valid_alert = 1 f. write en_meas_sys_valid_alert = 0 g. write force_meas_sys_on = 0 h. read updated measurement system data from the LTC4015 this procedure can be repeated at desired intervals (for example, once per second) in order to periodically moni - tor the system. thermistor /ntc measurement chosen thermistor at 25 c ( r25). ntc_ratio (0 x40) is available via the serial port, except when the ship mode feature has been activated. the LTC4015 measurement system is configured to directly calculate ntc_ratio, where: ntc_ratio= 21845 ? r ntc r ntcbias +r ntc r ntc =r ntcbias ? ntc_ratio 21845 Cntc_ratio ntc_ratio has a bit weight of 1/21845 = 4.5777 C5 /lsb. for a ntc_ratio of 0.5, where r ntc = r ntcbias , the value of ntc_ratio reported by the serial port would be approximately 10922. the data in the first two columns in the following table are from a vishay ntc thermistor with a r 25 of 10k and value of 3490 k, such as provided by a vishay ntcs0402e 3103flt or nths0402n 02n 1002je. the ntc_ratio value is 21845 ? [r ntc /( r ntc + r ntcbias )], where r ntcbias = r 25 = 10k. temperature r ntc ntc_ratio 10.0 18290 14122 15.0 14867 13059 20.0 12157 11985 25.0 10000 10922 30.0 8272 9889 35.0 6879 8902 40.0 5751 7975 steps to find ntc resistor temperature given a ntc_ratio value; 1. retrieve value for the ntc_ratio from the LTC4015 via the i 2 c port 2. calculate r ntc ; 3. using the calculated r ntc , use ntc resistor manufacturers data to determine temperature. battery temperature is sensed by using an external ntc (negative temperature coefficient) thermistor, r ntc . r ntc is normally located in the battery pack. connect r ntc between the ntc pin and ground. a bias resistor, r ntcbias , is connected between ntcbias and ntc. r ntcbias should be a 1% resistor with a value equal to the value of the r ntc =r ntcbias ntc_ratio 21845 Cntc_ratio ltc 4015 4015fb
22 for more information www.linear.com/LTC4015 operation icl, uvcl, icharge and vcharge dacs the LTC4015 has four dacs for setting target values of: 1. maximum battery charge voltage ( vcharge_ setting) 2. maximum battery charge current ( icharge _ target) 3. minimum input voltage, uvcl ( vin_ uvcl_ setting ) 4. maximum input current (iin_limit_set ting) the user can program the target values only with the i 2 c port. the LTC4015 uses the target values as a starting point, the charging algorithms calculate the actual values to be applied to the dacs to support functions such as li-ion precharge, absorb and equalize charge voltage adders, mppt, lead-acid charge voltage temperature compensa - tion, and charger soft starting. the target value register is read/write, the actual value register is read only. in the case of the uvcl register, minimum input voltage is scaled by external resistors. for further information see the register description and battery charging sections. jeita temperature controlled charging does not use vcharge_setting or icharge_target for setting target values, see jeita temperature controlled charging section for further information. charging timers there are a total of four timers in the LTC4015 used in the charging algorithms. timers are 16- bit, and measure time in seconds . 2 16 = 65535 seconds or 18.2 hours maximum. each timer has current value ( read only) and a timeout value (read/write): timed parameter current value timeout value applicable chemistries constant-voltage state time cv_timer (0x31) max_cv_time (0x1d) lithium chemistries maximum total charge time max_charge_ timer (0x30) max_charge_ time (0x1e) lithium chemistries maximum absorb charge time absorb_timer (0x32) max_absorb_ time (0x2b) lifep04, lead-acid maximum equalize charge t ime equalize_ timer (0x33) equalize_time (0x2d) lead-acid low power ship mode the LTC4015 can reduce its already low standby current to approximately 5 a in a special mode designed for shipment and storage. ship mode is armed by setting the arm_ship_mode register to 0x534d ( ascii for sm) via the serial port. note that once armed, ship mode cannot be disarmed ( the arm_ship_mode register cannot be cleared once set to 0 x534d). once armed, ship mode takes the target and actual registers as well as the dac size are shown below: function target value register actual value register name hex address (size) default name hex address (size) default input current limit iin_limit_setting 0x15(5:0) 0x3f iin_limit_dac 0x46(5:0) 0x3f battery charge voltage vcharge_setting 0x1b(5:0) 1 0x3f vcharge_dac 0x45(5:0) 0x3f minimum input voltage (uvcl) vin_uvcl_setting 0x16(8:0) 0xff scaled by external resistors battery charge current icharge_target 0x1a(4:0) 0x1f icharge_dac 0x44(4:0) 0x1f 1 lithium chemistries = 5b (4:0), lead-acid chemistry = 6b (5:0) ltc 4015 4015fb
23 for more information www.linear.com/LTC4015 operation effect when the input voltage drops below approximately 1v. upon return of the input voltage above approximately 1v the LTC4015 wakes from ship mode and all registers reset to their initial default values. the decision to remain out of ship mode is latched once the voltage reference is re-biased and intv cc is detected as having reached about 4.3v. upon exiting ship mode, all internal registers are reset to their default values. if the application requires that power be cut off from downstream system circuitry in ship mode, a second external pmos can optionally be added as shown in figure 2. unlike normal battery only mode, in ship mode the sysm5 pin is driven to the sys voltage to disable conduction through the second pmos. this action cuts off power to the downstream system, thus minimizing battery drain between product manufacture and sale. if the application does not require the battery to be isolated from downstream devices, significant power savings in the LTC4015 may still be realized by activating ship mode without the second pmos. figure 2. typical application with optional pmos added for ship mode cutoff LTC4015 v in uvclfb controller v in smbalert dv cc scl sda cells0 cells1 cells2 chem0 chem1 rt v c ccrefp ccrefm eq infet clp r sns1 cln sys sysm5 4015 f02 outfet system optional pmos added to cut off system load in ship mode intv cc drv cc boost tg sw bg 2p5v cc cspm5 csp csn r ntcbias r snsb batsens ntcbias ntc chemistry/ cell court selection lead-acid equalize charge (paddle) gnd sgnd mppt mppt enable r ntc battery pack t ltc 4015 4015fb
24 for more information www.linear.com/LTC4015 operation cells selection number of series cells selection is made using the cells2, cells1, and cells0 pins. for lithium chem - istries the LTC4015 allows charging of up to nine series cells. for lead-acid there are only three valid selections 3, 6 or 12 cells corresponding to 6, 12, and 24 v batteries respectively. note that number of cells multiplied by their expected maximum cell voltage during charging cannot exceed v in C 200 mv. with v in /v sys limited to 35 v as an upper bound for v bat , at nine cells the maximum v/cell would be 3.89 v. in practice the 3.89 v/cell will be lower, due to several factors including; input ideal diode drop (v in C v sys ) and switcher max duty cycle. these pins should be hard wired to gnd(l), intv cc (h), or left open (z). the LTC4015 does not monitor or balance individual cells C the full battery stack voltage is divided by number of cells (v/cell) for simplicity only. the 4015 is not a substitute for pack protection! number of cells cells2 cells1 cells0 invalid l l l 1 l l h 2 l h l 3 l h h 4 l l z 5 l z l 6 l h z 7 l z h 8 l z z 9 h l l invalid h l h invalid h h l 12* h h h * lead-acid only chemistry selection chemistry selection is made using the chem1 and chem0 pins. these are three-state pins used by the LTC4015 to select of one of nine chemistry specific charging algorithms. these pins should be hard wired to gnd(l), intv cc (h), or left open (z). chemistry chem1 chem0 li-ion programmable l l li-ion 4.2v/cell fixed h h li-ion 4.1v/cell fixed l z li-ion 4v/cell fixed z l lifepo 4 programmable l h lifepo 4 fixed fast charge h z lifepo 4 fixed standard charge z h lead-acid fixed z z lead-acid programmable h l li-ion/lifepo 4 battery charging it is the responsibility of the user of the LTC4015 to consult with the battery manufacturer to determine the recommended charging parameters for a particular battery . battery allowable temperature range while charging and any required charging parameter temperature coefficients also need to be considered. ltc 4015 4015fb
25 for more information www.linear.com/LTC4015 operation table 5. li-ion charging parameters charging algorithm icharge_ target v charge (per cell) cv timer term enable max cv time c/x term enable c/x thresh jeita max charge time low b at precharge current low b at threshold (per cell) li-ion programmable 32mv/ r snsb 1 4.20 1 yes 4 hours no 10% y 18 hrs ~10% 2 2.9v li-ion 4.2v/cell fixed 32mv/ r snsb 1 4.20 1 yes 4 hours no C y 18 hrs ~10% 2 2.9v li-ion 4.1v/cell fixed 32mv/ r snsb 1 4.10 1 yes 4 hours no C y 18 hrs ~10% 2 2.9v li-ion 4v/cell fixed 32mv/ r snsb 1 4.00 1 yes 4 hours no C y 18 hrs ~10% 2 2.9v li-ion/charging parameters table 5 shows li-ion charging parameters. for li-ion programmable, defaults values are shown. bold parameters are i 2 c programmable in li- ion programmable mode only. icharge _ target and vcharge_ setting values are at 25 c if jeita is en - abled 1 . shown in figure 3 is an example of a li- ion battery charging profile . shown in table 6 are the li- ion program - mable i 2 c configurable charging parameters. table 6. li-ion programmable i 2 c configurable parameters programmable mode parameter range bits resolution icharge_target 1 1mv to 32mv/ r snsb 5 1mv/r snsb vcharge_setting 1 3.8125v to 4.2v/cell 5 12.5mv max_cv_time 0 to 65535 16 1 second en_jeita 0, 1 1 1 = enable en_c_over_x_term 0, 1 1 1 = enable c_over_x_threshold 0mv to 32mv/ r snsb 16 1.465v/r snsb max_charge_time 0 to 65535 16 1 second notes 1) when jeita is enabled (en_jeita=1), icharge_target and vcharge_setting are controlled by the jeita temperature controlled charging algorithm, as described in the descriptions for icharge_ jeita_n and vcharge_jeita_n. 2) precharge current is 10% of icharge_target, rounded down to the next lsb. figure 3. li-ion 4.2v/cell fixed charging profile time (hr) v bat (v cell ) i chg (a) 4015 f03 4.5 4.0 3.0 2.5 2.0 1.5 1.0 0.5 3.5 0 12 9 6 3 0 0 1 4 5 6 32 v bat i chg cc_cv/cc cc_cv/cv 4hour cv timer termination text indicates values reported in registers: charger_state/charge_status ltc 4015 4015fb
26 for more information www.linear.com/LTC4015 operation lifepo 4 charging parameters table 7 shows lifepo 4 charging parameters. for lifepo 4 programmable, defaults values are shown. bold parameters are i 2 c programmable in lifepo 4 programmable mode only. icharge_target and vcharge_setting values table 7. lifepo 4 charging parameters charging algorithm icharge_ target v absorb , max_ absorb_ time in minutes v charge (per cell) cv timer term max cv time c/x term c/x thresh jeita max charge time lifepo 4 programmable 32mv/ r snsb 1 no absorb phase 3.60 1 yes 1 hour no 10% y 18 hrs lifepo 4 fixed standard charge 32mv/ r snsb 1 no absorb phase 3.60 1 yes 1 hour no C y 18 hrs lifepo 4 fixed fast charge 32mv/ r snsb 1 3.8, 15 3.60 1 yes 1 hour no 10% (absorb) y 18 hrs 1: when jeita is enabled icharge_target and vcharge_set ting are overridden and controlled by the jeita temperature qualified charging algorithm. are at 25 c when jeita is enabled. shown in table 8 are the lifepo 4 programmable i 2 c configurable charging parameters. shown in figure 4 is the lifepo 4 fixed fast charge charging profile. table 8. lifepo 4 programmable i 2 c configurable parameters programmable mode parameter range bits resolution icharge_target 1 1mv to 32mv/r snsb 5 1mv/r snsb vabsorb_delta 0v to 0.4v 5 12.5mv max_absorb_time 0 to 65535 16 1 second vcharge_setting 1 3.4125v to 3.8v/cell 5 12.5mv max_cv_time 0 to 65535 16 1 second en_jeita 0,1 1 1 = enable en_c_over_x_term 0,1 1 1 = enable c_over_x_threshold 0mv to 32mv/r snsb 16 1.465v/ r snsb max_charge_time 0 to 65535 16 1 second lifepo 4 _ recharge_ threshold 0 to 4.2 v/ cell 16 192.26v notes 1: when jeita is enabled icharge_target and vcharge_set ting are overridden and controlled by the jeita temperature qualified charging algorithm. figure 4. lifepo 4 fast charge charging profile time (min) v bat (v cell ) i chg (a) 4015 f04 4.5 4.0 3.0 2.5 2.0 1.5 1.0 0.5 3.5 0 12 9 6 3 0 0 5 20 25 30 1510 v bat i chg absorb/cc cc_cv/cv absorb/cv text indicates values reported in registers: charger_state/charge_status cv timer termination after one hour in cc_cv/cv phase ltc 4015 4015fb
27 for more information www.linear.com/LTC4015 operation li-ion/lifepo 4 battery charger operation the LTC4015 provides full featured, inherently safe , constant- current/ constant- voltage li-ion/ lifepo 4 battery charging. features include battery presence detection, automatic recharge, maximum charge time safety timer, precharge ( li-ion only), rapid absorb charge (lifepo 4 only), programmable cv timer and c/x termination, therm - istor temperature controlled charging, programmable end-of-charge indication, programmable charge voltage, programmable charge current, j.e.i.t.a. support, battery series resistance measurement, detailed status reporting, and programmable interrupt generation. LTC4015 charge algorithm overview the LTC4015 charge algorithms are based on a constant- current constant-voltage charging ( cc-cv)technique. the battery is charged at a constant-current ( cc) until the battery reaches its charge voltage (v charge ) whereupon the delivered charge current is automatically reduced to maintain the battery at a constant v charge ( cv). the LTC4015 does not monitor or balance individual cells C the full battery stack voltage is divided by number of cells (v/cell) for simplicity only. the 4015 is not a substitute for pack protection! under voltage current limiting ( uvcl) is used to automati - cally reduce charge current to help keep v in from falling below a minimum voltage. input current limiting ( icl) is used to automatically limit charge current to help keep input current below a maximum level. however, uvcl and icl can only reduce charge current. the total load current from v in cannot be limited by the LTC4015 if the load on the system exceeds the icl setpoint. li-ion charge algorithm overview (see figure 5 a for li-ion battery charging state diagram) the charge algorithm begins with a battery detection test and proceeds to constant-current constant-voltage (cc- cv) charging. if the li-ion battery voltage is very low the charger will charge at a reduced ( precharge) cc rate until the battery voltage reaches an acceptable level. then it will be charged at the full cc rate. cc-cv charging continues until the charge cycle terminates based on time ( default) or battery current (c/x for li-ion programmable option). lifepo4 charge algorithm (without absorption phase) overview ( see figure 5 b for lifepo 4 battery charging state diagram ) the charge algorithm begins with a battery detection test and proceeds to constant-current constant-voltage (cc- cv) charging. cc-cv charging continues until the charge cycle terminates based on time in cv mode ( default) or battery current (c /x for lifepo 4 programmable option). remaining in constant-voltage mode without termination is also a lifepo 4 programmable option. lifepo4 charge algorithm (with absorption phase) overview ( see figure 5 b for li- fepo 4 battery charging state diagram) an absorb phase can allow accelerated charging by raising the charge voltage, which may result in a higher cc rate, for a portion of the charge cycle. the charge algorithm begins with a battery detection test and proceeds to cc-cv charging with a charge voltage of v absorb , which is an absorb delta added to v charge . cc - cv absorption charging continues until the v absorb is reached and charge current has dropped below the c/x threshold, or the maximum absorb phase time has passed. upon exiting the absorb phase the charge voltage is reduced from v absorb to v charge . cc-cv charging continues until the charge cycle terminates based on time in cv mode ( default) or charge current (c/x) (lifepo 4 programmable option). remaining in constant-voltage mode without termination is also a lifepo 4 programmable option. ltc 4015 4015fb
28 for more information www.linear.com/LTC4015 operation figure 5a. li-ion battery charging state diagram charger_ suspended* battery detection shorted battery no battery 30 second time out bat_missing_ fault precharge battery voltage > 2.9 v/cell max_charge_time_fault max_charge_time passed v bat < 35% of v charge ntc_ratio between jeita_t7 and jeita_t1 * note: all states return to charger suspended if any of the following occur: a. the input voltage v in falls to within 100mv of the batsens pin voltage. b. suspend_charger is written to 1 via the serial port. c. a system fault occurs (v in overvoltage lockout, 2p5v cc undervoltage lockout, intv cc undervoltage lockout, drv cc undervoltage lockout. thermal shutdown, missing rt resistor, or invalid combination of cells pins). ntc_ratio below jeita_t7 or above jeita_t1 to ntc pause battery voltage > 2.85v/cell max_charge_timer starts c_over_x_term 4015 f05a max_cv_time passed with battery at v charge (cv) battery at v charge (cv) ?and? i chg < c_over_x_threshold ?and? en_c_over_x_term = 1 recharge threshold reached recharge threshold reached battery voltage stable battery voltage < 2.85 vcell cc_cv_charge bat_short_ fault ntc_pause ntc_ratio out of range to bat_missing_ fault return to previous charge state ntc_ratio below jeita_t7 or above jeita_t1 to ntc pause timer_term ltc 4015 4015fb
29 for more information www.linear.com/LTC4015 operation figure 5b. lifepo 4 battery charging state diagram charger_ suspended* battery detection shorted battery no battery 30 second time out bat_missing_ fault absorb charge absorb_time passed ?or? (absorb voltage reached and i chg < c_over_x_threshold) max_charge_time_fault max_charge_time passed v bat < 35% of v charge ntc_ratio between jeita_t7 and jeita_t1 * note: all states return to charger suspended if any of the following occur: a. the input voltage v in falls to within 100mv of the batsens pin voltage. b. suspend_charger is written to 1 via the serial port. c. a system fault occurs (v in overvoltage lockout, 2p5v cc undervoltage lockout, intv cc undervoltage lockout, drv cc undervoltage lockout. thermal shutdown, missing rt resistor, or invalid combination of cells pins). ntc_ratio below jeita_t7 or above jeita_t1 to ntc pause c_over_x_term 4015 f05a max_cv_time passed with battery at v charge (cv) ?and? not (max_cv_time = 0) battery at v charge (cv) ?and? i chg < c_over_x_threshold ?and? en_c_over_x_term = 1 recharge threshold reached recharge threshold reached battery voltage stable max_charge_timer starts vabsorb_delta > 0 absorb_timer starts cc_cv_charge bat_short_ fault ntc_pause ntc_ratio out of range to bat_missing_ fault return to previous charge state ntc_ratio below jeita_t7 or above jeita_t1 to ntc pause timer_term ltc 4015 4015fb
30 for more information www.linear.com/LTC4015 operation battery detection the LTC4015 begins a charging cycle by performing a two to four second battery detection test, during which a 1 ma load is drawn from the battery. if the battery volt - age remains stable during the battery detection test, the LTC4015 proceeds with battery charger soft-start. if the battery voltage does not remain stable, the LTC4015 proceeds with a battery open/short test. the battery is charged at minimum charge current for one to two seconds. if the battery voltage as a result of this brief charging is within a reasonable range the LTC4015 will proceed with a battery charger soft-start. a battery open fault will also occur if the ntc resistor is open or has a very high value. a programmable interrupt can be set to alert the system if a battery detection fault has occurred. battery charger soft-start the LTC4015 soft starts by ramping icharge_dac from 0 to icharge_target at a nominal rate of 400 s per icharge_target lsb. this results in a maximum soft- start time of 31 ? 400s = 12.4ms. maximum charge time the LTC4015, for charging batteries of lithium chemistries, provides a maximum charge time safety timer. the max _ charge_timer starts with the battery charger soft-start after battery detection. if the total time charging the battery exceeds max_charge_time, the charger will enter the max_charge_time fault state and cease charging. this fault state can only be exited in normal operation if the battery voltage is less than 35% of v charge , where upon a new charge cycle begins and the timer reset. the timer is reset upon timer or c/x termination. the max_charge_time fault state can also be exited as a result of the input voltage v in falling to within 100 mv of the batsens pin voltage, suspend_charger is written to a 1 via the serial port or a system fault occurs. low battery/pre-charge; li-ion when a li-ion battery charge cycle begins, the LTC4015 first determines if the battery is deeply discharged. if the battery voltage is below 2.85 v per cell (vbat_filt below 14822) and batsens pin is above 2.6 v then the LTC4015 begins charging by applying a preconditioning charge equal to icharge_target /10 ( rounded down to the next lsb), and reporting precharge = 1. when the battery voltage exceeds 2.9 v per cell ( vbat_filt above 15082), the LTC4015 proceeds to the constant-current/ constant-voltage charging phase (cc_cv_charge = 1). should the batsens pin voltage be lower than 2.4 v, the switching charger operates in constant peak current mode, where the peak current is 7mv/r snsb . exact average cur- rent value depends on a number of factors including input voltage, battery voltage and inductance value. when the batsens pin voltage is higher than 2.6v, normal charg - ing proceeds. low battery; lifepo 4 low battery for lifepo 4 chemistry is the same as li- ion with the exception that there is no precon- ditioning charge phase; charge current is set by icharge_target. however , if the ba tsens pin voltage is lower than 2.4v, the switching charger operates in constant peak current mode, where the peak current is 7 mv /r snsb . exact average current value depends on a number of factors including input voltage, battery voltage and inductance value. when the batsens pin voltage is higher than 2.6 v, normal charging proceeds. lifepo 4 absorb charge the LTC4015 can optionally perform an accelerated absorb charge cycle on lifepo 4 batteries. if vabsorb_delta is greater than zero, the LTC4015 begins charging with an absorb charge phase, and reports absorb_charge = 1 ltc 4015 4015fb
31 for more information www.linear.com/LTC4015 operation via the serial port. during absorb charging, the LTC4015 charges at a constant-current i chg , with a target set by icharge_target and r snsb , unless one of the following conditions occurs: a) the battery voltage reaches the absorb target voltage ( determined by vcharge_ setting + vabsorb_ delta, limited to a maximum of 3.8 v/cell), indicated by constant_voltage=1 b) input current limit ( iin_limit_setting) is reached, indicated by iin_limit_active=1 c) the uvclfb pin voltage falls to the undervoltage current limit ( vin_ uvcl_ setting) ), indicated by vin_ uvcl_ ac - tive=1 if either the input current limit or the undervoltage current limit is activated, the LTC4015 will limit charge current and will attempt to regulate at the input current or input voltage limit level, as permitted by the input source and system load. lifepo 4 absorb phase ends after either: a) max_absorb_time has passed b) the battery voltage reaches absorb target voltage (as determined by vcharge_ setting+ vabsorb_ delta, limited to a maximum of 3.8 v/ cell), indicated by constant_voltage=1, and ibat falls below c_over_x_ threshold. when the absorb phase ends, the LTC4015 proceeds to the cc-cv charging phase. constant-current/constant -voltage (cc-cv) charging constant-current when the battery voltage is above 2.9 v per cell, the charger will attempt to deliver the programmed charge current i chg , as set by icharge_target and r snsb , in constant-current mode. depending on available input power and external load conditions, the battery charger may not be able to charge at the full programmed rate. if input current limit is reached, the system load will always be prioritized over the battery charge current. likewise, the input undervoltage control loop will always be observed and may limit the power available to charge the battery. when system loads permit, battery charge current will be maximized. the upper limit of charge current i chg is programmed by the combination of the current sense resistor (r snsb ) from csp to csn and a servo voltage of 32 mv or a value programmed via the serial port ( see register descriptions for icharge_target and icharge_jeita_n). the voltage across r snsb divided by its value determines the maximum possible charge current. the maximum servo voltage that can be programmed is 32mv. a 4 m resistor, for example, would have an upper limit charge current of 8a. independent of whether or not the charge current loop is controlling the switching charger, the voltage across the r snsb will represent the actual charge current delivered to the battery. the voltage across r snsb is measured by the LTC4015s onboard measurement system and is available via the serial port in register ibat. r snsb should be set based on the maximum charge current of the battery without regard to source or load limitations from any other control loop. the multiple control loop architecture of the LTC4015 will correct for any discrepancies, always sorting out the optimal transfer of power to the battery. battery series resistance (bsr) measurement the LTC4015 can optionally measure the series resistance of the battery. if run_ bsr is set to 1 the LTC4015 momentarily suspends the battery charger and calculates the battery series resistance by dividing the change ( charging vs charger suspended ) in battery voltage by the change in charge current ( icharge_bsr). the per cell resistance value is reported in the bsr register and the change in charge current is reported in the icharge_bsr register via the serial port. the LTC4015 resets run_bsr to 0 after the bsr measurement is complete. the battery series resistance value is proportional to the charge current ltc 4015 4015fb
32 for more information www.linear.com/LTC4015 operation sense resistor, r snsb , and can be computed in from bsr ? r snsb /500. note that the resistance reported in the bsr register must be multiplied by the total number of cells to calculate total battery series resistance. the higher icharge_ bsr ( charge current) when a bsr measurement is requested, the more accurate the bsr measurement will be. very low values of icharge_bsr may significantly impact the accuracy of the bsr measurement. setting run_bsr to a 1 will not turn the charger on, if the charger is suspended or in a termination state, setting run_bsr = 1 results in the bsr measurement request being queued and run after the soft-start of the next charge cycle. battery charge voltage regulation, constant-voltage once the batsens voltage reaches the preset charge volt - age, the switching charger will reduce its output power, holding the battery voltage steady. the charge current will decrease naturally toward zero providing inherently safe operation by preventing the battery from being over- charged. multiple charge voltage settings are available for final charge voltage selection via the serial port. while charge voltage trade-offs can be made to preserve battery life or maximize capacity, it is not possible for the LTC4015 to be set to a charge voltage that is dangerously high or inconsistent with the batterys chemistry. li-ion lifepo 4 full capacity charge indication (c/x) and charger termination the battery charge cycle will terminate at the expiration of a built-in programmable cv termination safety timer (cv_timer). when the voltage on the battery reaches the programmed charge voltage, the safety timer is started. after the safety timer expires, charging of the battery will discontinue and no more current will be delivered. the safety timers default expiration time may be altered via the serial port. for li-ion cells the timer termination feature cannot be disabled. for lifepo 4 cells, timer termination can be disabled by setting max_cv_time to zero, in this case, if c/x termination is not enabled, charging will not terminate. c/x termination cannot be enabled in fixed chemistry algorithms. in addition, by monitoring the charge current and other states of the system, the LTC4015 determines when the battery has reached a given state of charge. specifically, programmable c/x detection in constant-voltage mode determines when the charge current has naturally dropped to a given fraction of its full - scale current. if c/x termination is enabled the charge cycle will end when c/x is reached, or when then safety timer expires, whichever occurs first. c/x termination is disabled by default. the LTC4015 can optionally be configured via the serial port to generate an interrupt and terminate charging when the c/x threshold is reached. the LTC4015 terminates charging by disabling the switch - ing controller, when this occurs the sw node goes hi z. li -ion lifepo4 automatic recharge after the battery charger terminates, it will remain off, drawing only a small amount of current from the battery. if the portable product remains in this state long enough, the battery will eventually self discharge. to ensure that the battery is always topped off, a new charge cycle will automatically begin when the battery voltage falls below approximately 97.5% of the programmed charge voltage for li-ion and 3.35 v/cell for lifepo 4 (3.35v/cell is the default for lifepo4_recharge_threshold in lifepo 4 programmable mode). the termination safety timer will also reset back to zero. a new charge cycle will also be initiated if input power is cycled or if the charger is momentarily disabled using the serial port ( suspend_charger set to 1, then set to 0). j.e.i.t.a. t emperature controlled charging for lithium chemistries, a measurement and control system has been included to enable compliance with the japan electronics and information technology industries association guidelines on battery charging. specifically a very flexible multi-point temperature-voltage-current ltc 4015 4015fb
33 for more information www.linear.com/LTC4015 operation profile can be programmed into the LTC4015 to ensure that optimum charging parameters as a function of temperature are always used. figure 6 illustrates an example of the jeita system available in the LTC4015. there are seven distinct temperature regions programmed by the six temperature set points jeita_t1-jeita_t6. for each of the temperature regions, the charge current and charge voltage can be programmed within the limits set by v cspCcsn /r snsb (i charge ) and battery charge voltage (v charge ) for a selected chemistry code. when jeita is enabled, charge current is controlled by icharge_dac, which in turn is set by icharge_jeita_n of the applicable jeita region. writing icharge_target has no effect, as it will be overwritten by jeita. likewise v charge is controlled by vcharge_dac which in turn is set by vcharge_jeita_n of the applicable jeita region. the LTC4015 provides temperature controlled charging if a grounded thermistor and a bias resistor are connected to the ntcbias and ntc pins. charging is paused if the temperature rises above a programmable upper limit or falls below a programmable lower limit. if the application does not require temperature controlled charging then the thermistor should be replaced with a resistor of equal value to bias resistor r ntcbias , for example, 10k. figure 6. default jeita temperature profile, showing values for li-ion fixed 4.2v temperature (c) v bat (v cell ) charge current (mv/r sense ) 4015 f06 4.5 t1 t2 t3 t5t4 t6 4.0 3.0 2.5 2.0 1.5 1.0 0.5 3.5 0 45 40 30 25 20 15 10 05 35 0 0 10 40 50 60 3020 charge voltage charge current the values for the jeita registers are shown in the tables below. the bold values in the tables are programmable when using li-ion programmable or lifepo 4 program- mable chemistry selections. the jeita_tn registers determine the ntc_ratio values for the breakpoints between regions. the corresponding temperature values assume a thermistor value of 3490k, such as provided by a vishay ntcs0402e3103 f lt or nths0402n02n1002je. for other thermistors, one or two inexpensive low temperature coefficient resistors can generally be added to the circuit to adjust the thermistors biasing ( see the section ntc resistor in applications information for details). table illustrates the jeita values that can be programmed via the serial port. region 1 region 2 region 3 region 4 region 5 region 6 region 7 jeita_t1 jeita_t2 jeita_t3 jeita_t4 jeita_t5 jeita_t6 charger off icharge _jeita_2 icharge_jeita_3 icharge_jeita_4 icharge_jeita_5 icharge_jeita_6 charger off vcharge_jeita_2 vcharge_jeita_3 vcharge_jeita_4 vcharge_jeita_5 vcharge_jeita_6 ltc 4015 4015fb
34 for more information www.linear.com/LTC4015 table default values for jeita parameters region 1 region 2 region 3 region 4 region 5 region 6 region 7 jeita_t1 = jeita_t2 = jeita_t3 = jeita_t4 = jeita_t5 = jeita_t6 = 0x3f00 (0c) 0x372a (10c) 0x1f27 (40c) 0x1bcc (45c) 0x18b9 (50c) 0x136d (60c) charger off icharge_jeita_2 icharge_jeita_3 icharge_jeita_4 icharge_jeita_5 icharge_jeita_6 charger off vcharge_jeita_2 vcharge_jeita_3 vcharge_jeita_4 vcharge_jeita_5 vcharge_jeita_6 li-ion programmable charger off 16 mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 4.20 v 4.20v 4.10v 4.10v 4.05v li-ion fixed 4.2v charger off 16 mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 4.20 v 4.20v 4.10v 4.10v 4.05v li-ion fixed 4.1v charger off 16 mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 4.10 v 4.10v 4.00v 4.00v 3.95v li-ion fixed 4.0v charger off 16 mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 4.00 v 4.00v 3.90v 3.90v 3.85v lifepo 4 programmable charger off 16mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 3.60 v 3.60v 3.50v 3.50v 3.45v lifepo 4 fixed fast and fixed standard charge charger off 16mv/r snsb 32mv/r snsb 32mv/r snsb 16mv/r snsb 16mv/r snsb charger off 3.60 v 3.60v 3.50v 3.50v 3.45v operation lead-acid battery charging it is the responsibility of the user of the LTC4015 to consult with the battery manufacturer to determine the recommended charging parameters for a particular battery . battery allowable temperature range while charging and any required charging parameter temperature coefficients also need to be considered. an example of charging profile ( battery voltage and cur - rent vs . time) for a lead-acid battery is shown in figure 7. lead-acid charging parameters following is a table of lead-acid charging parameters. for lead-acid programmable, default values are shown. bold parameters are programmable via the serial port in lead-acid programmable mode only . all voltages are per cell at 25c. figure 7. example charging profile for a lead-acid battery time (hrs) cc-cv/cv absorb/cv absorb/cc (also called bulk charging) text indicates values reported in registers: charger_state/charge_status equalize/cc equalize/cv v bat (v cell ) i chg (a) 4015 f07 3.0 2.5 2.0 1.5 1.0 0.5 0 12 8 6 4 2 10 0 0 1 32 t eq +2t eq t eq +4 v bat i chg cc-cv/cv ltc 4015 4015fb
35 for more information www.linear.com/LTC4015 operation undervoltage current limiting ( uvcl) is used to automati- cally reduce charge current to help keep v in from falling below a minimum voltage. input current limiting ( icl) is used to automatically limit charge current to help keep input current below a maximum level. however, uvcl and icl can only reduce charge current. the total load current from v in cannot be limited by the LTC4015 if the load on sys exceeds the icl setpoint. figure 8. lead-acid battery charging state diagram lead-acid charging parameters charging algorithm icharge_ target absorb c_over_x_ threshold v equalize , equalize time ( minutes) v absorb , max absorb time (minutes) end absorb on c/x v charge (per cell) mv/c tempco tempco enabled lead-acid fixed 32mv/r snsb 3.2mv/r snsb 2.60, 60 2.40, 90 yes 2.20 C3.65 yes lead-acid programmable 32mv/r snsb 3.2mv/r snsb 2.60,60 2.40, 90 yes 2.20 C3.65 yes programmable mode parameter range bits resolution icharge _t arget 1mv to 32mv/ r snsb 5 1mv/r snsb vcharge_setting 2v to 2.6v/cell 6 9.523mv vabsorb_delta 0v to 0.6v/cell 6 9.523mv vequalize_delta 0v to 0.6v/cell 6 9.523mv max_absorb_time 0 to 65535 16 1 second equalize_time 0 to 65535 16 1 second en_lead_acid_temp_comp 0, 1 1 1 = enable c_over_x_threshold 1 0mv to 32mv/ r snsb 16 1.465v/ r snsb notes 1: in lead-acid mode c_over_xthreshold is used only to terminate the absorb charge phase. lead-acid battery charger operation the LTC4015 provides full featured, inherently safe , constant - current / constant - voltage lead - acid battery charging with battery presence detection, equalization, absorb, bad battery detection, thermistor based charge voltage temperature compensation, programmable charge voltage, programmable charge current, battery series resistance measurement, detailed status reporting, and programmable interrupt generation. LTC4015 charge algorithm overview the LTC4015 charge algorithms are based on a constant- current constant-voltage charging (cc- cv) technique. the battery is charged at a constant-current ( cc) until the battery reaches its charge voltage (v charge ) whereupon the delivered charge current is automatically reduced to maintain the battery at a constant v charge (cv).the LTC4015 does not monitor or balance individual cells C the full battery stack voltage is divided by number of cells (v/cell) for simplicity only. the 4015 is not a substitute for pack protection! lead acid charge algorithm overview (see figure 8 for lead-acid battery charging state diagram) the charge algorithm begins with a battery detection test, then proceeds to cc-cv charging with a charge voltage charger_ suspended* battery detection no battery shorted battery bat_short_ fault * note: all states return to charger suspended if any of the following occur: a. the input voltage v in falls to within 100mv of the batsens pin voltage. b. suspend_charger is written to 1 via the serial port. c. a system fault occurs (v in overvoltage lockout, 2p5v cc undervoltage lockout, intv cc undervoltage lockout, drv cc undervoltage lockout. thermal shutdown, missing r t resistor, or invalid combination of cells pins). absorb_time passed with battery at absorb voltage ?or? (battery at absorb voltage and i chg < c_over_x_threshold) 4015 f08 battery voltage stable eq pin rising edge detected equalize_time passed ?or? eq pin falling edge detected absorb_charge cc_cv_charge equalize_ charge bat_missing_ fault 30 second timeout ltc 4015 4015fb
36 for more information www.linear.com/LTC4015 operation of v absorb , which is an absorb delta added to v charge . following constant- current bulk charging, constant - voltage absorption charging continues until v absorb is reached and charge current has dropped below the c/x threshold, or the battery absorb charge voltage is reached and the maximum absorb phase time has passed. if neither of the criteria for exiting the absorb charge phase is met then cc-cv charging with v absorb charge voltage can continue indefinitely. upon exiting the absorb phase the charge voltage absorb delta is set to zero and cc-cv float charging continues indefinitely. upon exiting the absorb phase an equalization charge can be performed upon user request. lead acid equalization charge the equalization charge voltage, v equalize , can be signifi- cantly higher than the absorption voltage. this aggressive over charging of the battery can equalize acid concentrations throughout the battery and remove electrode sulfation that may have formed during low charge conditions. equal- ization can restore battery capacity, but it can also result in battery heating, overcharging of some or all cells and the loss of electrolyte which can lead to battery damage. equalization is typically not performed with sealed batter- ies because they are usually not re-wettable in the event of electrolyte loss. due to its aggressive nature, specific equalization frequency, voltage and time duration should be obtained from the battery manufacturer. battery detection the LTC4015 begins a charging cycle by performing a two to four second battery detection test, during which a 1 ma load is drawn from the battery. if the battery volt- age remains stable during the battery detection test, the LTC4015 proceeds with battery charger soft-start. if the battery voltage does not remain stable, the LTC4015 proceeds with a battery open/short test. the battery is charged at minimum charge current for one to two seconds. if the battery voltage as a result of this brief charging is within a reasonable range the LTC4015 will proceed with a battery charger soft-start. a battery open fault will also occur if the ntc resistor is open or has a very high value. a programmable interrupt can be set to alert the system if a battery detection fault has occurred. battery charger soft-start the LTC4015 softs starts by ramping icharge_dac from minimum to icharge_ target at a nominal rate of 400s per icharge_target lsb. this results in a maximum soft-start time of 31 ? 400s = 12.4ms. low battery if the batsens pin voltage is lower than 2.4v , the switching charger operates in constant peak current mode, where the peak current is 7mv/r snsb . exact average current value depends on a number of factors including input voltage, battery voltage and inductance value. when the batsens pin voltage is higher than 2.6 v, normal charging proceeds. absorb charge the LTC4015 begins lead- acid battery charging with an absorb charge phase, and reports absorb_ charge = 1 via the serial port. during absorb charging, the LTC4015 charges at a constant- current i chg , with a target set by icharge_ target and r snsb , unless one of the following conditions occurs: a) the b attery voltage reaches the absorb target voltage ( v absorb )(determined by vcharge_ setting+vabsorb_delta, limited to a maximum of 2.6v/cell), indicated by constant_voltage=1 b) input current limit ( iin_limit_setting) is reached, indicated by iin_limit_active=1 c) the uvclfb pin voltage falls to the undervoltage current limit ( vin_uvcl_setting), indicated by vin_uvcl_ac - tive=1 if either the input current limit or the input undervoltage current limit is activated, the LTC4015 will limit charge current and will attempt to regulate at the input current limit or input undervoltage limit, as permitted by the input source and system load. absorb phase ends after the battery voltage reaches v absorb and either absorb_timer reaches max_ absorb_time or ibat falls below c_over_x_threshold. when the absorb phase ends, the LTC4015 proceeds to constant- current/constant-voltage (cc-cv) charge phase. constant-current/constant-voltage (cc-cv) charge: in cc-cv charging phase, the LTC4015 prevents the ltc 4015 4015fb
37 for more information www.linear.com/LTC4015 operation battery voltage from falling below the charge voltage level, as determined by vcharge_setting, unless one of the following conditions occurs: a) the battery charge current i chg reaches the target set by icharge_ target, indicated by constant_ current=1 b) input current limit ( iin_limit_setting) is reached, indicated by iin_limit_active=1 c) the uvclfb pin voltage falls to the undervoltage current limit ( vin_uvcl_setting), indicated by vin_uvcl_ac - tive = 1 if either the input current limit or the input undervoltage current limit is activated, the LTC4015 will limit charge current and will attempt to regulate at the input current limit or input undervoltage limit, as permitted by the input source and system load. there is no termination in the charging algorithm for lead-acid; the charger will remain in cv mode as long as input power is available. equalization charge: if a rising edge is detected on the eq pin ( as reported by the equalize_ req bit), the LTC4015 will perform an equalization charge when the charge voltage is reached (constant- voltage = 1) in constant-current/constant-voltage (cc-cv) charge phase. in equalization charging phase, the LTC4015 charges the battery at a constant- current i chg , with a target set by icharge_target and r snsb , unless one of the following conditions occurs: (a) the battery voltage reaches the equalization target voltage ( as determined by vcharge_ setting+vequalize_delta, limited to a maximum of 2.6v/cell), indicated by constant_voltage=1, (b) input current limit ( iin_limit_setting) is reached, indicated by iin_limit_active=1,or (c) the uvclfb pin voltage falls to the undervoltage current limit ( vin_ uvcl_ setting), indicated by vin_ uvcl_ ac - tive=1. if either the input current limit or the input undervoltage current limit is activated, the LTC4015 will limit charge current and will attempt to regulate at the input current limit or input undervoltage limit, as permitted by the input source and system load. equalize charge phase runs until equalize_ timer reaches equalize_ time, at which time the LTC4015 returns to constant- current/ constant- voltage (cc-cv) charge phase. the eq pin is rising edge triggered, it must remain high through the duration of the equalize phase. the eq pin must be de-asserted and re-asserted to begin another equalization charge. v in input power removal/suspend_charger/ system fault response if, at any time, the input voltage on the v in pin falls to within 100mv of the batsens pin voltage, or suspend_ charger is written to 1 via the serial port, or if a system fault condition occurs ( v in overvoltage, low 2 p5v cc voltage, low intv cc voltage, low drv cc voltage, thermal shutdown, missing r t resistor, or invalid combination of cells pins), the LTC4015 suspends charging and reports charger_ suspended = 1. battery series resistance (bsr) measurement the LTC4015 can optionally measure the series resistance of the battery. if run_ bsr is set to 1 the LTC4015 momentarily suspends the battery charger and calculates the battery series resistance. the per cell resistance value is reported in the bsr register and the change in charge current is reported in the icharge_ bsr register via the serial port. the battery series resistance value is proportional to the charge current sense resistor, r snsb , and can be computed in from bsr x r snsb /750. note that the resistance reported in the bsr register must be multiplied by the total number of cells to calculate total battery series resistance. the higher icharge_ bsr ( charge current) when a bsr measurement is requested, the more accurate the bsr measurement will be. very low values of icharge_ bsr may significantly impact the accuracy of the bsr measurement. setting run_ bsr to a 1 will not turn the charger on, if the charger is suspended or in a termination state. setting run_ bsr = 1 results in the bsr measurement request being queued and run after the soft- start of the next charge cycle. lead-acid temperature compensated charging (en_ lead_acid_temp_comp=1) the LTC4015 uses a C3.65 mv/ c per cell v charge temperature compensation when using a thermistor with a value of 3490 k similar to a vishay ntcs0402e3103flt or nths0402n02n1002je thermistor. when en_lead_ ltc 4015 4015fb
38 for more information www.linear.com/LTC4015 figure 9. lead-acid temperature profile temperature (c) charge voltage (v cell ) 4015 f09 2.7 2.6 2.5 2.4 2.3 2.2 1.9 2.1 2.0 ?50 1007550250?25 150125 cc?cv equalize absorb operation acid_temp_comp=1, the registers vcharge_setting, vabsorb_delta, and vequalize_delta control the 25c value of vcharge_dac. at other temperatures, the value of vcharge _ dac is adjusted based on ntc _ ratio , to produce the temperature profile shown in figure 9. in effect, the temperature profile is shifted up or down by increasing or decreasing the values of vcharge_ setting, vabsorb_delta, and vequalize_delta, but the slope of the temperature compensation response is not directly programmable. table default lead-acid temperature compensation parameter : registers that determine 25c value: default value at 25c (volts/ cell) v equalize vcharge_setting+vequalize_delta 2.6 v absorb vcharge_setting+vabsorb_delta 2.4 v charge vcharge_setting 2.2 coulomb counter the LTC4015 features an integrated coulomb counter for battery state of charge monitoring. charge is the time integral of current. the coulomb counter is disabled by default, and can be enabled only via the i 2 c port (en_qcount). there are several i 2 c accessible registers associated with the coulomb counter. the lo and hi alerts listed below can be disabled. see register map and detailed register descriptions for details. en_qcount 1-bit enable coulomb counter (0x14, bit 2) en_qcount_lo_alert 1-bit enable coulomb counter low alert. (0xod bit 13) en_qcount_hi_alert 1-bit enable coulomb counter high alert. (0xod bit 12) qcount 16-bits coulomb counter accumulator value (0x13) qcount_lo_ alert_limit 16-bits coulomb counter accumulator low alert limit. (0x10) qcount_hi_ alert_limit 16-bits coulomb counter accumulator high alert limit. (0x11) qcount_ prescale_factor 16-bits coulomb counter prescale factor. (0x12) the LTC4015 does not directly sense battery current, but instead senses v cspCcsn developed across r snsb . this voltage is divided by the value of r snsb to calculate cur- rent. the coulomb counter integrates v cspCcsn to infer charge. the differential voltage across r snsb is applied to a voltage to the frequency converter ( v-to-f). when the integrator portion of the v- to -f output ramps to the ccrefp or ccrefm level, switches s1, s2, s3 and s4 toggle to reverse the ramp direction. by observing the state of the switches and the ramp direction, polarity is determined. the frequency of this ticking is directly proportional to v csp- csn . the coulomb counter v- to -f transfer function is: f tick = k qc ? v csp C csn the LTC4015 limits lead-acid charge voltage to 2 v to 2.6v/ cell regardless of battery temperature in cc-cv, absorb and equalize modes. vabsorb_delta is an adder to vcharge_ setting in absorb mode. vequalize _ delta is an adder to vcharge_setting in equalize mode. at 25 c the default charge voltage is 2.2 v/ cell. using C3.65 mv/c per cell, v charge will reach its minimum of 2.0v/ cell at a temperature of 80 c. similarly, v charge reaches its maximum of 2.6v/cell at a temperature of C85c. the default vabsorb_delta value is 0x15 (21 decimal). this translates to an absorb voltage of 2.4 v/cell at 25c. the default vequalize_ delta value is 0 x2a (42 decimal). this translates to an equalize voltage of 2.6 v/cell at 25c. temperature compensation is active over a ntc_ratio range of 21437 to 912, which corresponds to an ap- proximate te mper ature range of C55 c to 135 c using a thermistor with a value of 3490 k such as the vishay ntcs 0402e3103 f lt or nths0402n02n1002je. see figure 9. ltc 4015 4015fb
39 for more information www.linear.com/LTC4015 operation where k qc = 8333.33hz/v f tick is then divided by a prescaler (qcount_prescale_ factor) that is programmable from 1 to 65535 ( default of 512). the prescaler effectively increases integration time by a factor equal to qcount_prescale_factor. at each under or overflow of the prescaler, the accumulated voltage register ( qcount) is incremented or decremented one count. the value of accumulated voltage is read via the i 2 c interface. to achieve the specified precision of the coulomb counter the differential voltage v cspCcsn must stay within 50mv. for differential input signals up to 300mv the coulomb counter will remain functional but the precision of the coulomb counter is not guaranteed. the value of external sense resistor, r snsb , influences the gain of the coulomb counter. a larger sense resistor gives a larger differential voltage for the same current which results in more precise coulomb counting. thus the amount of charge represented by the least significant bit (q lsb ) of the accumulated charge is given by: q lsb = qcount_prescale_factor k qc ?r snsb q lsb units are in coulombs (amp-seconds) where: k qc = 8333.33hz/v qcount_prescal_factor = value of the prescaler r snsb is in ? if the value of qcount reaches 0 or 65535, the value saturates. qcount does not wrap. as long as input power is applied and the battery charger is enabled, the LTC4015 will allow lead-acid batteries to remain in a cv state indefinitely. as the battery slowly discharges itself internally, the LTC4015 replenishes the lost charge, and this charge is accumulated by the coulomb counter. after a long period of time, the coulomb counter accumulated charge due to battery self discharge current while the charger is in cv mode could cause significant errors relative to the actual soc of the battery. coulomb counter applications the following examples demonstrate simple applications of the LTC4015 coulomb counter function. for more advanced applications, including calibration of state- of- charge based on temperature, please contact linear technology applica - tions engineering for more information. example : setting qcount_prescale_factor and initializing and calibrating qcount: charging two li-ion 3.5ah batteries in parallel at 6.4a total total capacity = 7.0 ah = 7.0a ? 3600sec = 25200c constant-current charging at 6.4 a requires r snsb = 32mv/6.4a = 5m the maximum value of the qcount register is 65535. to prevent over ranging qcount, the highest allowed value of q lsb is 25200c/65535 = 0.385c using: q lsb = qcount_prescale_factor k qc ?r snsb r snsb csp s1 ccrefm 4015 f10 ccrefp control logic polarity detection s2 s3 s4 charger battery csn gnd i bat ? + ? + ? + + prescalar m to LTC4015 logic/ serial port figure 10. coulomb counter section of the LTC4015 ltc 4015 4015fb
40 for more information www.linear.com/LTC4015 operation in order to achieve a q lsb of at least 0.385 c, qcount_ prescale_factor must be at least q lsb ? (k qc ? r snsb ) = 0.385 ? (8333.33 ? 0.005). doubling ( to allow for margin) and rounding to the nearest integer gives qcount_prescale_factor = 32. the initial state of charge ( soc) of the battery is known to be approximately 25%. given that the qcount_ prescale_factor = 32 has now been set for ap - proximately twice the capacity of the battery, the desired valid range of qcount is from 16384 ( to represent 0% soc) to 49152 ( to represent 100% soc). the value of qcount is thus initialized to (32768 ? 0.25) + 16384 = 24576 to represent the approximate 25% initial soc. in this case, the soc of the battery at any time can be calculated as 100% ? (qcountC16384)/32768. upon the first termination ( c_ over _x_ term=1 or timer_term=1), the battery is known to be very near 100% soc, so the value of qcount can be calibrated accordingly. for example, if the initial state of charge was actually 23% instead of the expected 25%, termina - tion will occur when qcount is approximately 49806. upon the first termination, the value of qcount is over written to 49152 to calibrate qcount to the true soc of the battery. example: coulomb counter charge termination the coulomb counter alert limits can be used to imple- ment a maximum state of charge termination algorithm. the following example demonstrates such a procedure: 1) set the coulomb counter register ( qcount) to the battery's initial state of charge, and set qcount_ prescale_factor based on the battery capacity, as indicated in the example above. 2) set qcount _ hi_ alert_ limit to the desired maximum state of charge of the battery ( e.g . qcount_ hi_ alert_ limit = 49152) 3) set en_qcount_hi_alert=1 4) if the battery charges enough that qcount exceeds qcount_hi_alert_limit, the LTC4015 will issue an smbalert and set qcount_ hi_ alert=1. after completing the alert response algorithm and verifying that the LTC4015 is issuing qcount_hi_alert=1, set suspend_charger=1 to stop the battery from charging. at this time, write qcount_lo_alert_limit to a lower level corresponding to a recharge threshold (e.g. qcount_lo_alert_limit = 0.95 ? qcount_ hi_alert_limit) and set en_qcount_lo_alert=1 and en_qcount_hi_alert=0. 5) when the battery discharges enough that qcount falls below qcount_lo_alert_limit, the LTC4015 will issue an smbalert and set qcount_lo_alert=1. after completing the alert response algorithm and verifying that the ltc 4015 is issuing qcount_lo_alert=1, set e n_ qcount _ lo _ alert=0, en _ qcount _ hi _ alert=1, and suspend_ charger=0 to allow the battery to charge again. step down switching charger controller the LTC4015s primary power path is a fully synchronous step down switching charger controller. due to its all nmos design, a diode and capacitor are required to provide high side boosted drive. taking error signals from four control loops simultaneously, the feedback paths are externally compensated with a rc network connected to the v c pin. the switching controller is designed to charge single or multiple batteries. normal charging proceeds at a constant- current until the batteries reach their target voltage. the maximum charge current is determined by the value of the sense resistor, r snsb , used in series with the inductor. the charge current loop servos the voltage across r snsb to the value determined by icharge_dac. when charging is enabled an internal soft-start will ramp up the charge current from zero to icharge_target. both the battery voltage and charge current can be read back over i 2 c. the LTC4015 provides constant power charging by limiting input current drawn by the switching controller. the input current limit will reduce charge current to limit the voltage across the input sense resistor, r snsi , to iin_limit_setting. if the combined system load plus battery charge current is large enough to cause the switching controller to reach the programmed input current limit, the input current limit loop will reduce the charge current. even if the charge current is programmed to exceed the allowable input current, the input current will not be violated; the charger will reduce its current as needed. the input current can be read back over i 2 c. ltc 4015 4015fb
41 for more information www.linear.com/LTC4015 drv cc the bottom gate driver is powered from the drv cc pin. drv cc is normally connected to the intv cc pin. an external ldo or dc/dc converter can also be used to power the top and bottom gate driver to minimize power dissipa - tion inside the ic. the use of a dc/dc for d rv cc can also minimize power dissipation in general. intv cc / drv cc and ic power dissipation the LTC4015 features an internal pmos low dropout linear regulator ( ldo) that supplies power to intv cc from v sys . intv cc powers the gate drivers (when drv cc is connected to intv cc ) and much of the LTC4015s internal circuitry. the intv cc ldo regulates the voltage at the intv cc pin to 5 v. the ldo can supply a maximum current of 50ma and must be bypassed to ground with a ceramic capacitor with a minimum value of 4.7 f. if drv cc is not connected to intv cc , it should have at least a 2.2 f ceramic or low esr electrolytic capacitor. no matter what type of bulk capacitor is used on drv cc , an additional 0.1 f ceramic capacitor placed directly adjacent to the drv cc pin and gnd is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC4015 to be exceeded. the drv cc current, which is dominated by the gate charge current, is supplied by the intv cc ldo. power dissipation for the ic in this case is highest and is approximately equal to ( v sys ) ? ( i q + i g ), where i q is the non-switching quiescent current of ~4ma and i g is gate charge current. the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics. for example, the i g supplied by the intv cc ldo is limited to less than 42ma from a 35v supply in the qfn package at a 70 c ambient temperature: t j = 70c + (35v)(4ma + 42ma)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the drv cc current must be checked while oper- ating in continuous conduction mode at maximum v sys . the power dissipation in the ic is significantly reduced if drv cc is powered from an external ldo. in this case the power dissipation in the ic is equal to power dissipation due to i q and the power dissipated in the gate drivers, (vdrv cc ) ? (i g ). assuming the external drv cc ldo out- put is 5 v and is supplying 42 ma to the gate drivers, the junction temperature rises to only 82c: t j = 70 c + [(35 v )(4ma)+(5 v )(42ma)](34 c/w) = 82c if d rv cc is powered from an external ldo, the ldo should be powered from v sys and its output must be less than 5.5v. in this case, drv cc should not be tied to intv cc . sequencing is also important, if drv cc is not tied to intv cc , drv cc should not be applied until intv cc has reached 3v to ensure the gate drivers are held off. die temperature sensor the LTC4015 has an integrated die temperature sensor. it is monitored by the adc and is digitized to the die_temp register. an alarm may be set on die temperature by setting the die_temp_lo_alert_limit and/or die_temp_hi_ alert_limit registers and enabling the alarms in the en_limit_alerts register. intv cc and drv cc uvlo internal undervoltage lockout circuits monitor both the intv cc and drv cc pins. the switching controller is kept off until intv cc rises above 4.3 v and drv cc is above 4.2v. hysteresis on the uvlos turn off the controller if either intv cc falls below 4 v or drv cc falls below 3.9v. charging is not enabled until v in is 200 mv above the bat- tery voltage . charging is disabled when v in falls to within 100mv of the battery voltage. input overvoltage protection the LTC4015 has overvoltage detection on its input. if v in exceeds 38.6 v, the switching controller will hold both switches off. the controller will resume switching if v in falls below 37.2v. operation ltc 4015 4015fb
42 for more information www.linear.com/LTC4015 ntc resistor selection applications information mately mimic the profile of a thermistor value of 3490k over the range C40 to 125 c, resulting in less than 5c of error ( typical) for the lead-acid temperature charging profile ( see lead-acid temperature compensated charg - ing), which in turn results in a battery voltage error of less than 20mv/cell over temperature. setting the r t resistor a resistor on the rt pin sets the LTC4015s step down regulator switching frequency. to keep the inductor size down and ensure optimum efficiency and stability the LTC4015 switching frequency can be optimized ( see in - ductor selection section). an r t value of 95.3 k resistor sets the frequency to 500khz: f osc(mhz) = 47.65 r t (k?) setting input and charge currents as mentioned previously, maximum average charge current is determined by the value of the sense resistor r snsb , connected between csp and csn, which is in series with the inductor. the maximum average input current is de - termined by the resistance r snsi , connected between the clp and cln pins. the input and charge current loops servo the voltages across their respective sense resistors to a maximum of 32 mv. therefore the maximum input and charge average currents are: i in(max ) = 32mv r snsi i chg(max ) = 32mv r snsb compensation the input current, charge current, v bat voltage and uvcl voltage loops all require a 6.8 nf to 14.7 nf capacitor from the v c node to ground. when using the mppt feature with resistive sources in excess of 0.5, the required v c capacitor (c vc ) may be in the 100' s of nf, with an additional series resistor in the 100 to 1000 range. if a series r is used, a smaller cap, c vc /10, should be placed directly from v c to ground. with minor modifications to the thermistor bias network, it is possible to adjust the effective temperature profile of the thermistor. note that this technique can generally only reduce the slope of the temperature profileit is not possible to increase the sensitivity of the thermistor. the temperature based charging characteristics of the LTC4015 are based on the adc reading ntc_ratio. for the alternate thermistor bias network shown in figure 11, the value of ntc_ratio is determined by: ntc_ratio= 21845 ? r ntceff r ntcbias +r ntceff the values of r ntcbias , r parallel , and r series can be selected in order to achieve a desired temperature profile for ntc_ratio. note that thermistor temperature profiles are highly nonlinear; consult manufacturers documenta - tion for data on a specific thermistor. tw o examples are included here as a demonstration example 1: for a lithium chemistry battery with a 100k vishay nths0402n 01n 1003 j ntc thermistor, using r ntcbias =100 k, r parallel = 2 m, and r series = 5 k will approximately mimic the profile of a thermistor value of 3490 k over the range 0 c to 60 c, resulting in less than 1c of error ( typical) for the default jeita temperature thresholds ( defined by jeita_tn, see jeita temperature controlled charging). this error is significantly less than the error tolerance of most thermistors. example 2: for a lead-acid battery with a 100 k vishay nths0402n01n1003j ntc thermistor, using r ntcbias = 95k, r parallel = 5 m, and r series = 2 k will approxi- figure. 11 4015 f11 r ntcbias r series r parallel ntcbias ntc t r ntc thermistor r ntceff = 1 1 r parallel + 1 r ntc +r series ltc 4015 4015fb
43 for more information www.linear.com/LTC4015 applications information if testing is to be done with a electronic load in constant- current mode, care must be taken if using cc mode that instability may occur. a few milli farads on v bat , with enough series r ( e.g. esr) to give a zero around 1khz range can help in this situation. inductor selection the operating frequency and inductor selection are interre - lated. higher operating frequencies allow the use of smaller inductor and capacitor values but generally also results in lower efficiency because of mosfet switching and gate charge losses. in addition, the effect of inductor value on ripple current must also be considered. the inductor ripple current decreases with higher inductance or higher frequency and increases with higher v in . accepting larger values of ripple current allows the use of low inductances, but results in higher output voltage ripple and greater core losses. for the LTC4015, the best overall performance will be attained if the inductor is chosen to be: l = v bat 1C v bat / v in(max) ( ) 0.25 ? f ?i chg(max) where v bat is the highest batsens voltage, v in(max) is the maximum input voltage, i chg(max) is the maximum regulated charge current and f sw is the switching fre- quency. using these equations, the inductor ripple will be at most 25% of i chg(max) . once the value for l is known, the type of inductor core must be selected. ferrite cores are recommended for their very low core loss. selection criteria should concentrate on minimizing copper loss and preventing saturation. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this causes an abrupt increase in inductor ripple current and consequent out - put voltage ripple. do not allow the core to saturate! the saturation current for the inductor should be at least 60% higher than the maximum regulated current, i chg(max) . c sys and c b at capacitance the specification for c sys will be determined by the desired ripple voltage: ?v sys = v bat v sys 1? v bat v sys ? ? ? ? i chg(max) c sys ? f sw +i chg(max) ? esr csys in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v bat /v sys ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms =i chg(max) v bat v sys v sys v bat C 1 this formula has a maximum at v sys = 2 v bat , where i rms = i chg(max) /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. medium voltage (20v to 35 v) ceramic, tantalum, os-con and switcher rated electrolytic capacitors can be used as input capacitors. sanyo os-con svp, svpd series; sanyo poscap tqc series or aluminum electrolytic capacitors from panasonic wa series or cornel dublilier spv series, in parallel with a couple of high performance ceramic capacitors, can be used as an effective means of achieving low esr and high bulk capacitance. the purpose of the v bat capacitor is to filter the induc- tor current ripple as well as to stabilize the charger if the batter y is not present or has high bsr. the v bat ripple (v bat ) is approximated by: v bat = i p-p 1 8 ?c bat ? f sw +esr cbat ? ? ? ? ? ? where f sw is the operating frequency, c bat is the ca- pacitance on v bat and i p-p is the ripple current in the inductor. the output ripple is highest at maximum input voltage since i p-p increases with input voltage. power mosfet selection tw o external power mosfets must be selected for the LTC4015s synchronous controller: one n-channel mos - fet for the top switch and one n-channel mosfet for the bottom switch. the selection criteria of the external n- channel power mosfets include maximum drain - source voltage (v dss ), threshold voltage, on-resistance (r ds(on) ), reverse transfer capacitance (c rss ), total gate charge (q g ) and maximum continuous drain current. v dss should be selected to be higher than the maxi- ltc 4015 4015fb
44 for more information www.linear.com/LTC4015 mum input supply voltage ( including transient) for both mosfets. the peak-to-peak drive levels are set by the drv cc voltage. logic-level threshold mosfets must be used because drv cc is powered from either intv cc (5v) or an external ldo whose output voltage must be less than 5.5v. mosfet power losses are determined by r ds(on) and c rss and q g . the conduction loss at maximum charge current for the top mosfet switches are: p cond(top) = v bat v sys ?i chg(max) 2 ?r ds (on) ? ? ? ? ? ? 1+ t ( ) p cond(bot) = 1? v bat v sys ? ? ? ? ? ? i chg(max) 2 ?r ds (on) ? ? ? ? ? ? 1+ t ( ) the term (1+ t) is generally given for a mosfet in the form of a normalized r ds( on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. both mosfet switches have conduction loss . however, transition loss occurs only in the top mosfet in step-down converter. this loss is proportional to v sys 2 and can be considerably larger in high voltage applications (v sys > 20v). the maximum transition loss is: p tran = k/2 ? (v sys ) 2 ? i chg(max) ? c rss ? f sw where k is related to the drive current during the miller plateau and is approximately equal to one. choosing a high side mosfet that has a higher r ds (on) and lower crss can minimize overall losses; by reducing transition losses more than the corresponding conduction loss increase. another power loss related to switching mosfet selection is the power lost to driving the gates. the total gate charge, q g , must be charged and discharged each switching cycle. the power is lost to the internal ldo and gate drivers within the LTC4015. the power lost due to charging the gates is: pg = (q gtop + q gbot ) ? f sw ? v sys schottky diode selection optional schottky diodes can be placed in parallel with the top and bottom mosfet switches. these diodes clamp sw during the non-overlap times between conduction of the top and bottom mosfet switches. this prevents the body diodes of the mosfet switches from turning on, storing charge during the non-overlap time and requir- ing a reverse recovery period that could cost as much as 3% in efficiency at high v in . one or both diodes can be omitted if the efficiency loss can be tolerated. the diode can be rated for about one-half to one-fifth of the full load current since it is on for only a fraction of the duty cycle. larger diodes result in additional switching losses due to their larger junction capacitance. in order for the diodes to be effective, the inductance between them and the top and bottom mosfets must be as small as possible. this mandates that these components be placed next to each other on the same layer of the pc board. top mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the top mosfet. capacitor c b in figure 12 is charged though external diode, d b , from drv cc when the sw pin is low. the value of the bootstrap capacitor, c b , needs to be 20 times that of the total input capacitance of the top mosfet. the bypass capacitor on drv cc should be at least 10 times the value of c b . applications information figure 12. bootstrap capacitor/diode and drv cc connections 4015 f12 boost sw drv cc 0.1f > 2.2f d b c b intv cc LTC4015 1f with the top mosfet on, the boost voltage is above the system supply rail: v boost = v sys + v drvcc . the reverse break down of the external diode, d b , must be greater than v sys (max) + v drvcc (max). d b can be either a schottky diode or a fast switching pn diode. care must be taken to not exceed the maximum ltc 4015 4015fb
45 for more information www.linear.com/LTC4015 boost-sw voltage of 5.5 v which may be possible with a schottky under certain conditions, particularly if the step down charger is operating asynchronously. fast switching pn diodes are recommended due to their low leakage and junction capacitance. minimum on-time considerations minimum on-time, t on (min), is the smallest time dura- tion that the LTC4015 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. the minimum on-time for the LTC4015 is approximately 85ns. low duty cycle applications may approach this minimum on-time limit. if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the v bat voltage will continue to be regulated, but the ripple voltage and current will increase. if cycling skipping is undesirable care should be taken to ensure that: v bat v sys ? f sw > t on (min) = 85ns ideal diode mosfet selection an external n- channel mosfet is required for the input ideal diode and a p- channel mosfet for output ideal diode. important parameters for the selection of these mosfets are the maximum drain- source voltage, v dss , gate thresh- old voltage and on- resistance ( r ds( on) ). when the input is grounded the battery stack voltage is applied across the input ideal diode mosfet. when v bat is at 0 v , the input voltage is applied across the output ideal diode mosfet. therefore , the v dss of the input ideal diode mosfet must withstand the maximum voltage on v bat while the v dss of output ideal diode mosfet must withstand the highest voltage on v in . the gate drive for both ideal diodes is 5 v . this requires the use of logic- level threshold p and n- channel mosfets. as a general rule, select mosfets with a low enough r ds( on) to obtain the desired v ds while operating at full load current. the LTC4015 will regulate the forward voltage drop across the input and output ideal diode mosfets at 15mv if r ds( on) is low enough. the required r ds( on) can be calculated by dividing 15mv by the load current in amps. achieving forward regulation will minimize power loss and heat dissipation, but it is not a necessity. if a forward volt- age drop of more than 15 mv is acceptable then a smaller mosfet can be used, but must be sized compatible with the higher power dissipation. care should be taken to ensure that the power dissipated is never allowed to rise above the manufacturers recommended maximum level. uvclfb resistor divider selection the LTC4015 input undervoltage current limit ( uvcl) function regulates voltage at the uvclfb pin based on the value programmed in the vin_uvcl_setting register. do not write to the vin_uvcl_setting register when mppt is enabled. if mppt is enabled, the uvclfb input voltage resistor divider must be set to 10 k and 294 k for the bottom and top resistors, respectively. resistor tolerance should be 1% or better. these resistor values result in a gain of 30.4 from the uvclb pin to v in . the 1.2 v maximum servo level at uvclfb would require the minimum v in at the maximum servo voltage to be greater than 1.2v ? 30.4 = 36.48 v, which is above the LTC4015s maximum v in . this is necessary to allow the mppt algorithm to search across the entire v in range. if maximum power point tracking ( mppt) is not enabled, the default undervoltage setting of vin_uvcl_setting = 0 xff sets the uvclfb undervoltage servo level to 1.2v. in this case, the input voltage resistor divider should be chosen such that uvclfb = 1.2v when v in is slightly above the higher of 4.3v or v bat(max) , to prevent undervoltage lockout ( uvlo). for example, for a two cell li- ion application, the bottom and top resistors in the uvclfb divider could be chosen as 75 k and 470 k, respectively, which sets the input undervoltage regulation limit at 8.72 v. note that when mppt is disabled, and the mppt uvclfb 10k and 294 k resistor divider values are used, the default vin_uvcl_setting of 1.2 v will result in the LTC4015 not charging the battery. the undervoltage regulation feature can be disabled. the uvclfb pin is clamped, the clamp begins to engage at 2v nominally. care must be taken to keep switching noise from coupling on to the uvclfb pin, a capacitor to signal gnd may be required. applications information ltc 4015 4015fb
46 for more information www.linear.com/LTC4015 1. connect uvclfb to 2 p5v cc through a 10 k resistor. this method results in an additional 25 a to 50 a battery current drain when v in < v bat as the 2p5v cc ldo is powered by v bat is this condition. 2. alternatively, the uvclfb pin can be tied to v in through an appropriately sized resistor which keeps the pin cur- rent below 200 a. this method results in zero battery current draw when v in < v bat . the 294 k mppt uvclfb divider top resistor would meet this requirement. when a uvclfb input voltage resistor divider is present, if maximum power point tracking is disabled, input undervoltage regulation can be prevented by setting vin_uvcl_setting to its lowest value (0x00). uvcl and mppt when available input power is low the LTC4015 battery charger function requires a minimum amount of current to operate, which varies depending on the application ( switching mosfet selection, compensation, etc). if the maximum input current available from the v in supply is above 2 ma to 3 ma but below the minimum level required to operate the charger ( generally approximately in the range 5 ma to 20 ma) then the battery may actually be discharged slightly by the charger. under these conditionsfor example, a very dimly lit ( but not completely dark) solar panel the worst- case battery drain current is generally less than 10 ma, and persists only as long as the available input current from the v in source remains in this range. if the available input current falls to below 2 ma to 3 ma, then the battery discharge returns to near normal battery only mode levels. as such, if the input source is a solar panel, this battery drain will generally be short-lived and infrequent enough ( for example, for a brief period shortly before sunrise and after sunset) as to be insignificant. however, if this drain is a concern, it can be mitigated by disabling the charger ( setting suspend_ charger=1) whenever i chg falls below 1% of full-scale (ibat <= 218), and retrying ( writing suspend_charger=0) periodically ( e.g. every 60 seconds). optionally, this retry can be limited to only occur when v in is above a known good threshold. pcb layout considerations when laying out the printed circuit board, the following guidelines should be used to ensure proper operation of the ic. check the following in your layout: 1. keep m 1, m 2, d 1, d 2 and c sys close together. the high di/ dt loop formed by the mosfet s, schottky diodes and c sys shown in figure 13 should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. surface mount components are preferred to reduce parasitic inductances from component leads. connect the drain of the top mosfet and cathode of the top diode directly to the positive terminal of c sys . connect the source of the bottom mosfet and anode of the bottom diode directly to the negative terminal of c sys . this capacitor provides the ac current to the mosfets . 2. gnd is referenced to the negative terminal of the v bat decoupling capacitor. the negative terminal of c sys should be as close as possible to negative terminal of c bat by placing the capacitors next to each other and away from the switching loop described above. the combined ic ground pin/paddle and the ground return of c intvcc and c drvcc must return to the combined negative terminals of c sys and c bat . 3. effective grounding techniques are critical for success- ful dc /dc converter layouts. orient power components such that switching current paths in the ground plane do not cross through the gnd pin and exposed pad on the backside of the LTC4015. switch path currents can be controlled by orienting the mosfet switches, schottky diodes, the inductor, and v sys and v bat decoupling capacitors in close proximity to each other. 4. route csp and csn sense lines together, keep them short. place a 1 nf ceramic capacitor across csp-csn as close as possible to the LTC4015. filter components should be placed near the part and not near sense resistor. ensure accurate current sensing with kelvin connections at the sense resistors. see figure 14. 5. route clp and cln sense lines together, keep them short. filter components should be placed near the part and not near sense resistor. ensure accurate current sensing with kelvin connections at the sense resistors. see figure 15. applications information ltc 4015 4015fb
47 for more information www.linear.com/LTC4015 6. locate the d rv cc and boost decoupling capacitors in close proximity to the ic. these capacitors carry the mosfet drivers high peak currents. an additional 0.1 f ceramic capacitor placed immediately next to the drv cc pin can help improve noise performance substantially. 7. locate the small signal components away from high frequency switching nodes ( boost, sw, tg, and bg). all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC4015. applications information 8. the input ideal diode senses the voltage between v in and v clp . v in should be connected near the source of the input ideal diode mosfet. v clp is used for kelvin sensing the input current. place the input current sense resistor, r snsi , near the input ideal diode mosfet with a short, wide trace to minimize resistance between the drain of the ideal diode mosfet and r snsi . 9. the output ideal diode senses the voltage between v sys and v csp . v sys should be connected near the source of the output ideal diode mosfet. v csp is used for kelvin sensing the charge current. place the output ideal diode near the charge current sense resistor, r snsb , with a short, wide trace to minimize resistance between the drain of the ideal diode mosfet and r snsb . LTC4015 digital system this section provides a detailed explanation of the func - tions of the LTC4015 digital system available via the serial port registers. LTC4015 digital system usage examples 1, 2 t he following usage examples describe applications which demonstrate a range of functionality available with the LTC4015 system. note that these examples represent only a small fraction of the LTC4015s full digital functionality. LTC4015 digital system usage example 1: coulomb counter and low limit alert only upon initial power up with an embedded battery in a known state of charge, the serial port master writes the LTC4015 bit en_qcount=1, enabling the coulomb counter. register qcount is initialized to reflect the known state of charge, qcount_prescale_factor is written for optimum range and resolution, qcount _ lo_ alert_ limit is written to a value known to correspond to a critical low state of charge, and en_qcount_lo_alert is written to 1. if the state of charge falls below the level defined by qcount_lo_alert_limit, the LTC4015 pulls down the smbalert pin. the serial port master performs an alert response algorithm ( ara) which confirms that the LTC4015 is the source of the alert and causes the LTC4015 to release the smbalert pin. the master then reads the v sys v bat c sys d1 d2 l1 r snsc m n1 m n2 4015 f13 c bat bat1 bat2 high frequency circulating path r snsc or r snsi to csp or clp to csn or cln 4015 f15 r snsc or r snsi to csp or clp to csn or cln 4015 f14 figure 13. high speed switching path figure 14. kelvin current sensing figure 15. kelvin current sensing ltc 4015 4015fb
48 for more information www.linear.com/LTC4015 limit_alerts register to confirm that qcount_lo_alert is true. the master then initiates appropriate system action (e.g. emergency power down, user warning, etc). see the sections coulomb counter, programmable inter - rupt controller , and detailed register descriptions for more details. LTC4015 digital system usage example 2: custom bat - tery charger settings for a lead-acid battery pack with batter y overtemperature alert. the LTC4015 chem1 and chem0 pins are strapped to select the chemistry algorithm. upon initial power-up, the serial port master writes suspend_charger=1, then writes vcharge_ setting, vabsorb _ delta, max _ absorb_ time, vequalize _ delta, and equalize_ time based on the battery manufacturers recommendation for charge voltage and time. the master writes ntc_ratio_ lo_ alert_ limit to the value of ntc_ ratio which corresponds to the maximum safe charging temperature for the battery pack and ntc thermistor, and writes en_ntc_ratio_lo_alert = 1. the master then re-enables the battery charger by writing suspend_charger=0. at regular long intervals ( for example, every 30 days) the master optionally initiates an equalization charge by as - serting the eq pin. if the thermistor temperature ever exceeds the level corresponding to ntc_ ratio_ lo_ alert_ limit, the ltc 4015 pulls down the smbalert pin. the serial port master then performs an ara which confirms that the LTC4015 is the source of the alert and causes the LTC4015 applications information to release the smbalert pin. the master reads the limit_alerts register to confirm that ntc_ratio_lo_alert is true. the master then writes suspend_charger=1 to disable the battery charger. optionally, in order to detect when the battery temperature has returned to a safe level for charging, the master writes ntc_ratio_hi_alert_limit to a value corresponding to 5 c below the maximum safe charging temperature of the battery, and writes en_ntc_ratio_hi_alert=1. when the thermistor temperature falls below this level, the LTC4015 generates a new smbalert for ntc_ratio_hi_alert=1, which is again confirmed by the master. the master then disables the alert by writing en_ ntc_ ratio_ hi_ alert=0, clears ntc_ratio_lo_alert ( by writing a 0 to that bit), then re-enables the charger by writing suspend_charger=0. see the sections lead-acid battery charge algorithm, programmable interrupt controller, and detailed register descriptions for more details. LTC4015 digital system usage example 3: battery charger state monitoring the serial port master writes en_charger_suspended_ alert=1 to generate an alert if the battery charger is ever disabled ( e.g. due to the removal of v in input power). if v in input power is removed, the LTC4015 pulls down the smbalert pin and sets the charger_suspended bit to 1. after performing an ara, the serial port master directs the system to minimize battery drain ( e.g. dimming displays, powering down unnecessary functions, etc). ltc 4015 4015fb
49 for more information www.linear.com/LTC4015 register description serial port register map. all bits are active high. registers are unsigned except where noted. all registers contain 16 bits. unused register bits as well as registers 0x17, 0x18, 0x49 are reserved and should not be written. symbol sub addr r/w active bits description default page vbat_lo_alert_limit 0x01 r/w 15:0 battery voltage low alert limit, signed, same format as vbat (0x3a) 0x0000 55 vbat_hi_alert_limit 0x02 r/w 15:0 battery voltage high alert limit, signed, same format as vbat (0x3a) 0x0000 55 vin_lo_alert_limit 0x03 r/w 15:0 input voltage low alert limit, signed, same format as vin (0x3b) 0x0000 55 vin_hi_alert_limit 0x04 r/w 15:0 input voltage high alert limit, signed, same format as vin (0x3b) 0x0000 55 vsys_lo_alert_limit 0x05 r/w 15:0 output voltage low alert limit, signed, same format as vsys (0x3c) 0x0000 55 vsys_hi_alert_limit 0x06 r/w 15:0 output voltage high alert limit, signed, same format as vsys (0x3c) 0x0000 55 iin_hi_alert_limit 0x07 r/w 15:0 input current high alert limit, signed, same format as iin (0x3d) 0x0000 55 ibat_lo_alert_limit 0x08 r/w 15:0 charge current low alert limit, signed, same format as ibat (0x3e) 0x0000 55 die_temp_hi_alert_limit 0x09 r/w 15:0 die temperature high alert limit, signed, same format as die_ temp (0 x3f) 0x0000 55 bsr_hi_alert_limit 0 x0a r/w 15:0 battery series resistance high alert limit, signed, same format as bsr (0x41) 0x0000 55 ntc_ratio_hi_alert_limit 0x0b r/w 15:0 thermistor ratio high ( cold battery) alert limit, signed, same format as ntc_ ra tio (0x40) 0x0000 55 ntc_ratio_lo_alert_limit 0x0c r/w 15:0 thermistor ratio low (hot battery) alert limit, signed, same format as ntc_ratio (0x40) 0x0000 55 en_limit_aler ts 0x0d r/w 15:0 enable limit monitoring and alert notification via smbalert 0x0000 56 en_meas_sys_valid_alert 0x0d r/w 15 enable meas_sys_valid_alert (0x36) 0 56 0x0d r/w 14 reserved 0 en_qcount_low_alert 0x0d r/w 13 enable qcount_low_alert (0x36) 0 56 en_qcount_high_alert 0x0d r/w 12 enable qcount_high_alert (0x36) 0 56 en_vbat_lo_alert 0x0d r/w 11 enable vbat_lo_alert (0x36) 0 56 en_vbat_hi_alert 0x0d r/w 10 enable vbat_hi_alert (0x36) 0 56 en_vin_lo_alert 0x0d r/w 9 enable vin_lo_alert (0x36) 0 56 en_vin_hi_alert 0x0d r/w 8 enable vin_hi_alert (0x36) 0 56 en_vsys_lo_alert 0x0d r/w 7 enable vsys _lo_alert (0x36) 0 56 en_vsys_hi_alert 0x0d r/w 6 enable vsys_hi_alert (0x36) 0 56 en_iin_hi_alert 0x0d r/w 5 enable iin_hi_alert (0x36) 0 56 en_ibat_lo_alert 0x0d r/w 4 enable ibat_lo_alert (0x36) 0 57 en_die_temp_hi_alert 0x0d r/w 3 enable_die_temp_hi_alert (0x36) 0 57 en_bsr_hi_alert 0x0d r/w 2 enable bsr_hi_alert (0x36) 0 57 en_ntc_ratio_hi_alert 0x0d r/w 1 enable ntc_ratio_hi alert (cold battery; 0x36) 0 57 en_ntc_ratio_lo_alert 0x0d r/w 0 enable ntc_ratio_lo_alert (hot battery; 0x36) 0 57 en_charger_state_alerts 0x0e r/w 15:0 enable charger state alert notification via smbalert 0x0000 57 en_equalize_charge_alert 0x0e r/w 10 enable lead-acid equalize_charge_ alert (0x37) 0 57 en_absorb_charge_alert 0x0e r/w 9 enable absorb_charge_alert (0x37) 0 57 en_charger_suspended_alert 0x0e r/w 8 enable charger_suspended_alert (0x37) 0 57 en_precharge_alert 0x0e r/w 7 enable precharge_alert (0x37) 0 57 en_cc_cv_charge_alert 0x0e r/w 6 enable cc_cv_charge_alert (0x37) 0 57 ltc 4015 4015fb
50 for more information www.linear.com/LTC4015 register description symbol sub addr r/w active bits description default page en_ntc_pause_alert 0x0e r/w 5 enable ntc_pause_alert (0x37) 0 58 en_timer_term_alert 0x0e r/w 4 enable timer_term_alert (0x37) 0 58 en_c_over_x_term_alert 0x0e r/w 3 enable c_over_x_term alert (0x37) 0 58 en_ max_ charge_ time_ fault_ alert 0x0e r/w 2 enable max_charge_time_fault alert (0x37) 0 58 en_bat_missing_fault_alert 0x0e r/w 1 enable bat_missing_fault alert (0x37) 0 58 en_bat_short_fault_alert 0x0e r/w 0 enable bat_short_fault alert (0x37) 0 58 en_charge_status_alerts 0x0f r/w 15:0 enable charge status alert notification via smbalert 0x0000 58 en_vin_uvcl_active_alert 0x0f r/w 3 enable vin_uvcl_active_alert (v in undervoltage current limit; 0x38) 0 58 en_iin_limit_active_alert 0x0f r/w 2 enable iin_limit_active_alert (i in current limit; 0x38) 0 58 en_constant_current_alert 0x0f r/w 1 enable constant_current_alert (0x38) 0 58 en_constant_voltage_alert 0x0f r/w 0 enable constant_voltage_alert (0x38) 0 58 qcount_lo_alert_limit 0x10 r/w 15:0 coulomb counter qcount low alert limit, same format as qcount (0x 13) 0x0000 59 qcount_hi_alert_limit 0x11 r/w 15:0 coulomb counter qcount high alert limit, same format as qcount (0x 13) 0x0000 59 qcount_prescale_factor 0x12 r/w 15:0 coulomb counter prescale factor 0x0200 59 qcount 0x13 r/w 15:0 coulomb counter value 0x8000 59 config_bits 0x14 r/w 15:0 configuration settings 0x0000 59 suspend_charger 0x14 r/w 8 suspend battery charger operation 0 59 run_bsr 0x14 r/w 5 perform a battery series resistance measurement 0 59 force_meas_sys_on 0x14 r/w 4 force measurement system to operate 0 59 mppt_en_i2c 0x14 r/w 3 enable maximum power point tracking 0 59 en_qcount 0x14 r/w 2 enable coulomb counter 0 59 iin_limit_setting 0x15 r/w 5:0 input current limit setting = (iin_limit_setting + 1) ? 500v / r snsi 0x3f 60 vin_uvcl_setting 0x16 r/w 7:0 uvclfb input undervoltage limit = (vin_ uvcl_ setting + 1) ? 4.6875mv 0xff 60 reserved 0x17 reserved 0x18 arm_ship_mode 0x19 r/w 15:0 write 0x534d to arm ship mode. once armed, ship mode cannot be disarmed. 0x0000 60 icharge_target 0x1a r/w 2 4:0 maximum charge current target = (icharge_ target + 1) ? 1mv /r snsb see note 1 60 vcharge_setting 0x1b r/w 2 5:0 charge voltage target. see detailed description for equations. see note 1 60 c_over_x_threshold 0x1c r/w 2 15:0 tw o s complement low ibat threshold for c/x termination see note 1 61 max_cv_time 0x1d r/w 2 15:0 time in seconds with battery charger in the cv state before timer termination occurs (lithium chemistries only) see note 1 62 max_charge_time 0x1e r/w 2 15:0 time in seconds before a max_charge_time fault is declared. set to zero to disable max_charge_time fault see note 1 62 jeita_t1 0x1f r/w 2 15:0 value of ntc_ratio for transition between jeita regions 2 and 1 (off) 0x3f00 62 ltc 4015 4015fb
51 for more information www.linear.com/LTC4015 register description symbol sub addr r/w active bits description default page jeita_t2 0x20 r/w 2 15:0 value of ntc_ratio for transition between jeita regions 3 and 2 0x372a 62 jeita_t3 0x21 r/w 2 15:0 value of ntc_ratio for transition between jeita regions 4 and 3 0x1f27 62 jeita_t4 0x22 r/w 2 15:0 value of ntc_ratio for transition between jeita regions 5 and 4 0x1bcc 62 jeita_t5 0x23 r/w 2 15:0 value of ntc_ratio for transition between jeita regions 6 and 5 0x18b9 62 jeita_t6 0x24 r/w 2 15:0 value of ntc_ratio for transition between jeita regions 7 (off) and 6 0x136d 62 vcharge_jeita_6_5 0x25 r/w 2 9:0 vcharge values for jeita temperature regions 6 and 5 see note 1 62 vcharge_jeita_6 9:5 63 vcharge_jeita_5 4:0 63 vcharge_jeita_4_3_2 0x26 r/w 2 14:0 vcharge values for jeita temperature regions 4, 3, and 2 see note 1 62 vcharge_jeita_4 14:10 63 vcharge_jeita_3 9:5 63 vcharge_jeita_2 4:0 63 icharge_jeita_6_5 0x27 r/w 2 9:0 icharge_target values for jeita temperature regions 6 and 5 0x01ef 63 icharge_jeita_6 9:5 0x0f 63 icharge_jeita_5 4:0 0x0f 63 icharge_jeita_4_3_2 0x28 r/ w 2 14:0 icharge_target value for jeita temperature regions 4, 3, and 2 0x7fef 63 icharge_jeita_4 14:10 0x1f 63 icharge_jeita_3 9:5 0x1f 63 icharge_jeita_2 4:0 0x0f 63 charger_config_bits 0x29 r/w 2 2:0 battery charger configuration settings, bits 15:3 are reserved. see note 1 63 en_c_over_x_term 2 enable c/x termination see note 1 63 en_lead_acid_temp_comp 1 enable lead-acid charge voltage temperature compensation see note 1 63 en_jeita 0 enable jeita temperature profile see note 1 63 vabsorb_delta 0x2a r/w 2 5:0 lifepo 4 /lead-acid absorb voltage adder, bits 15:6 are reserved. see note 1 61 max_absorb_time 0x2b r/w 2 15:0 maximum time for lifepo 4 /lead-acid absorb charge see note 1 62 vequalize_delta 0x2c r/w 2 5:0 lead-acid equalize charge voltage adder, bits 15:6 are reserved. 0x002a 61 equalize_time 0x2d r/w 2 15:0 lead-acid equalization time 0x0e10 62 lifep04_recharge _ threshold 0x2e r/w 15:0 lifep0 4 recharge threshold 0x4410 62 reserved 0x2f max_charge_timer 0x30 r 15:0 for lithium chemistries, indicates the time (in sec) that the battery has been charging 64 cv_timer 0x31 r 15:0 for lithium chemistries, indicates the time (in sec) that the battery has been in constant-voltage regulation 64 absorb_timer 0x32 r 15:0 for lifepo 4 and lead-acid batteries, indicates the time (in sec) that the battery has been in absorb phase 64 equalize_timer 0x33 r 15:0 for lead-acid batteries, indicates the time (in sec) that the battery has been in equalize phase 64 ltc 4015 4015fb
52 for more information www.linear.com/LTC4015 register descriptions symbol sub addr r/w active bits description default page charger_ state 0x34 r 15:0 real time battery charger state indicator. individual bits are mutually exclusive. bits 15:11 are reserved. 64 equalize_charge 10 indicates battery charger is in lead-acid equalization charge state 64 absorb_charge 9 indicates battery charger is in absorb charge state 64 charger_suspended 8 indicates battery charger is in charger suspended state 64 precharge 7 indicates battery charger is in precondition charge state 64 cc_cv_charge 6 indicates battery charger is in constant-current constant-voltage state 64 ntc_pause 5 indicates battery charger is in thermistor pause state 65 timer_term 4 indicates battery charger is in timer termination state 65 c_over_x_term 3 indicates battery charger is in c/x termination state 65 max_charge_time_fault 2 indicates battery charger is in max_charge_time_fault state 65 bat_missing_fault 1 indicates battery charger is in missing battery fault state 65 bat_short_fault 0 indicates battery charger is in shorted battery fault state 65 charge_status 0x35 r 15:0 charge status indicator. individual bits are mutually exclusive. only active in charging states. 65 vin_uvcl_active 3 indicates the input undervoltage control loop is actively controlling power delivery based on vin_uvcl_setting (0x16) 65 iin_limit_active 2 indicates the input current limit control loop is actively controlling power delivery based on iin_limit_dac (0x46) 65 constant_current 1 indicates the charge current control loop is actively controlling power delivery based on icharge_dac (0x44) 65 constant_voltage 0 indicates the battery voltage control loop is actively controlling power delivery based on vcharge_dac (0x45) 65 limit_aler ts 0x36 r 15:0 limit alert register. individual bits are enabled by en_limit_alerts (0x0d). writing 0 to any bit clears that alert. once set, alert bits remain high until cleared or disabled. 65 meas_sys_valid_alert 15 indicates that measurement system results have become valid. 66 qcount_lo_alert 13 indicates qcount has fallen below qcount_ lo_ alert_ limit (0x 10) 66 qcount_hi_alert 12 indicates qcount has exceeded qcount_hi_alert_limit (0x11) 66 vbat_lo_alert 11 indicates vbat has fallen below vbat_lo_alert_limit (0x01) 66 vbat_hi_alert 10 indicates vbat has exceeded vbat_hi_alert_limit (0x02) 66 vin_lo_alert 9 indicates vin has fallen below vin_lo_alert_limit (0x03) 66 vin_hi_alert 8 indicates vin has exceeded vin_hi_alert_limit (0x04) 66 vsys_lo_alert 7 indicates vsys has fallen below vsys_lo_alert_limit (0x05) 66 vsys_hi_alert 6 indicates vsys has exceeded vin_hi_alert_limit (0x06) 66 iin_hi_alert 5 indicates iin has exceeded iin_hi_alert_limit (0x07) 66 ibat_lo_alert 4 indicates ibat has fallen below ibat_lo_alert_limit (0x08) 66 die_temp_hi_alert 3 indicates die_ temp has exceeded die_ temp_ hi_ alert_ limit (0x 09) 67 bsr_hi_alert 2 indicates bsr has exceeded bsr_hi_alert_limit (0x0a) 67 ltc 4015 4015fb
53 for more information www.linear.com/LTC4015 register descriptions symbol sub addr r/w active bits description default page ntc_ratio_hi_alert 1 indicates ntc_ratio has exceeded ntc_ratio_hi_alert_limit (cold battery; 0x0b) 67 ntc_ratio_lo_alert 0 indicates ntc_ratio has exceeded ntc_ratio_lo_alert_limit (hot battery; 0x0c) 67 charger_state_aler ts 0x37 r 15:0 charger state alert register. individual bits are enabled by en_charger_state_alerts (0x0e). writing 0 to any bit clears that alert. once set, alert bits remain high until cleared or disabled. 67 equalize_charge_alert 10 alert indicates charger has entered lead- acid equalize_ charge state (0x 34) 67 absorb_charge_alert 9 alert indicates charger has entered absorb_charge state (0x34) 67 charger_suspended_alert 8 alert indicates charger has entered charger_ suspended( off) state (0x 34) 67 precharge_alert 7 alert indicates charger has entered precharge charge state (0x34) 67 cc_cv_charge_alert 6 alert indicates charger has entered cc_ cv_ charge state ( constant- current constant-voltage; 0x34) 67 ntc_pause_alert 5 alert indicates charger has entered ntc_pause state (0x34) 67 timer_term_alert 4 alert indicates charger has entered timer_term state (0x34) 67 c_over_x_term_alert 3 alert indicates charger has entered c_over_x term state (c/x termination; 0x34) 67 max_charge_time_fault_alert 2 alert indicates charger has entered max_ charge_ time_ fault state (0x 34) 68 bat_missing_fault_alert 1 alert indicates charger has entered bat_missing_fault state (0x34) 68 bat_short_fault_alert 0 alert indicates charger has entered bat_short_fault state (0x34) 68 charge_status_alerts 0x38 r 5:0 alerts that charge_status indicators have occurred individual bits are enabled by en_charge_status_alerts (0x0f) writing 0 to any bit clears that alert. once set, alert bits remain high until cleared or disabled. 68 vin_uvcl_active_alert 3 alert indicates vin_uvcl_active state entered (v in undervoltage current limit, 0x35) 68 iin_limit_active_alert 2 alert indicates iin_limit_active state entered (v in current limit; 0x35) 68 constant_current_alert 1 alert indicates constant_current state entered (0x35) 68 constant_voltage_alert 0 alert indicates constant_voltage state entered (0x35) 68 system_status 0x39 r 15:0 real time system status indicator bits 68 charger_enabled 13 indicates that the battery charger is active 68 mppt_en_pin 11 indicates the mppt_ en pin is set to enable maximum power point tracking 68 equalize_req 10 indicates a rising edge has been detected at the eq pin, and an lead- acid equalize charge is queued 68 drvcc_good 9 indicates drv cc voltage is above switching charger undervoltage lockout level (4.3v typical) 69 cell_count_error 8 indicates an invalid combination of cells pin settings 69 ok_to_charge 6 indicates all system conditions are met to allow battery charger operation 69 no_rt 5 indicates no resistor has been detected at the rt pin 69 thermal_shutdown 4 indicates die temperature is greater than thermal shutdown level (160 c typical) 69 ltc 4015 4015fb
54 for more information www.linear.com/LTC4015 symbol sub addr r/w active bits description default page vin_ovlo 3 indicates vin voltage is greater than overvoltage lockout level (38.6v typical) 69 vin_gt_vbat 2 indicates vin voltage is sufficiently greater than batsens for switching charger operation (200mv typical) 69 intvcc_gt_4p3v 1 indicates intv cc voltage is above switching charger undervoltage lockout level (4.3v typ) 69 intvcc_gt_2p8v 0 indicates intv cc voltage is greater than measurement system lockout level (2.8v typical) 69 vba t 0x3a r 15:0 tw o s complement adc measurement result for the batsens pin. v batsens /cellcount = [vbat] ? 192.264v for lithium chemistries. v batsens /cellcount = [vbat] ? 128.176v for lead-acid. 69 vin 0x3b r 15:0 tw o s complement adc measurement result for v in . v vin = [vin] ? 1.648mv 69 vsys 0x3c r 15:0 tw o s complement adc measurement result for v sys . v sys = [vsys] ? 1.648mv 69 ibat 0x3d r 15:0 tw o s complement adc measurement result for (v csp C v csn ). charge current (into the battery) is represented as a positive number. battery current = [ibat] ? 1.46487v/r snsb 69 iin 0x3e r 15:0 tw o s complement adc measurement result for (v clp C v cln ). input current = [iin] ? 1.46487v/r snsi 70 die_temp 0 x3f r 15:0 tw o s complement adc measurement result for die temperature. temperature = (die_temp C 12010)/45.6c 70 ntc _ra tio 0x40 r 15:0 tw o s complement adc measurement result for ntc thermistor ratio. r ntc = ntc_ratio ? r ntcbias /(21845.0 C ntc_ratio) 70 bsr 0x41 r 15:0 calculated battery series resistance. for lithium chemistries, series resistance/cellcount = bsr ? r snsb /500.0 for lead- acid chemistries, series resistance/ cellcount = bsr ? r snsb /750.0 70 jeita_region 0x42 r 2:0 jeita temperature region of the ntc thermistor (li only). active only when en_jeita=1 70 chem_cells 0x43 r 11:0 readout of chem and cells pin settings 70 chem 11:8 programmed battery chemistry 70 reserved 7:4 reserved cell_count_pins 3:0 cell count as set by cells pins 70 icharge_dac 0x44 r 4:0 charge current control dac control bits 71 vcharge_dac 0x45 r 5:0 charge voltage control dac control bits 71 iin_limit_dac 0x46 r 5:0 input current limit control dac control word 71 vbat_filt 0x47 r 15:0 digitally filtered twos complement adc measurement result for battery voltage 71 icharge_bsr 0x48 r 15:0 this 16-bit two's complement word is the value of ibat (0x3d) used in calculating bsr. 71 reserved 0x49 meas_sys_valid 0x4a r 0 measurement valid bit, bit 0 is a 1 when the telemetry(adc) system is ready 71 notes : 1. some defaults are chemistr y dependant. see the detailed register descriptions for more information. 2. charger setting registers (sub-addresses 0x1a through 0x2d) are only writable if the chem pins are configured for a programmable chemistry option. if the chem pins are configured for a fixed chemistry option, the charger setting registers are read only. register descriptions ltc 4015 4015fb
55 for more information www.linear.com/LTC4015 detailed register descriptions vbat_lo_alert_limit (sub-address 0x01, bits 15:0, r/w), vbat_hi_alert_limit (sub-address 0x02, bits 15:0, r/w) these 16- bit words set upper and lower limits that can be used to trigger an smbalert based on the batsens pin voltage out of range. the values use the same twos complement format as vbat. for lithium chemistries, batsens/ cellcount voltage hi/lo alert limit = [vbat_xx_alert_limit] ? 192.264 v. for lead-acid batteries, batsens/cellcount voltage hi/lo alert limit = [vbat_xx_alert_limit] ? 128.176v vin_lo_alert_limit (sub-address 0x03, bits 15:0, r/w), vin_hi_alert_limit (sub-address 0x04, bits 15:0, r/w) these 16- bit words set upper and lower limits that can be used to trigger an smbalert based on input voltage at the v in pin out of range. the values use the same twos complement format as vin. input voltage hi/lo alert limit = [vin_xx_alert_limit] ? 1.648mv. vsys_lo_alert_limit (sub-address 0x05, bits 15:0, r/w), vsys_hi_alert_limit (sub-address 0x06, bits 15:0, r/w) these 16- bit words set upper and lower limits that can be used to trigger an smbalert based on system voltage at the sys pin out of range. the values use the same twos complement format as vsys. system voltage hi/lo alert limit = [vsys_xx_alert_limit] ? 1.648mv. iin_hi_alert_limit (sub-address 0x07, bits 15:0, r/w) this 16- bit word sets an upper limit that can be used to trigger an smbalert based on input current above a certain value. iin_hi_alert_limit uses the same twos complement format as iin. input current high alert limit = [iin_hi_ alert_limit] ? 1.46487v/r snsi . ibat_lo_alert_limit (sub-address 0x08, bits 15:0, r/w) this 16- bit word sets an upper limit that can be used to trigger an smbalert based on charge current below a certain value. ibat_lo_alert_limit uses the same twos complement format as ibat with battery discharge current being negative. battery current low alert limit = [ibat_lo_alert_limit] ? 1.46487v/r snsb . die_temp_hi_alert_limit (sub-address 0x09, bits 15:0, r/w) this 16- bit word sets an upper limit that can be used to trigger an smbalert based on high die temperature. die_ temp_hi_alert_limit uses the same twos complement format as die_temp. ltc 4015 temperature = (die_temp C 12010)/45.6c bsr_hi_alert_limit (sub-address 0x0a, bits 15:0, r/w) this 16- bit word sets an upper limit that can be used to trigger an smbalert based on high battery series resistance. bsr_hi_alert_limit uses the same format as bsr. the battery series resistance is a function of r snsb , and can be computed as /cellcount = [bsr/500] ? r snsb ( lithium chemistries), or /cellcount = [bsr/750] ? r snsb (lead-acid). ntc_ratio_hi_alert_limit (sub-address 0x0b, bits 15:0,r/w), ntc_ratio_lo_alert_limit (sub-address 0x0c, bits 15:0, r/w) these 16- bit words set upper and lower limits that can be used to trigger an smbalert based on thermistor value out of range. the values use the same twos complement format as ntc_ratio. the thermistor value can be determined by the expression r ntc = r ntcbias ? ntc_ratio/(21,845 C ntc_ratio). recall that the thermistor has a negative temperature coefficient so higher temperatures correspond to lower ntc_ratio readings and vice-versa. thus, ntc_ratio_hi_alert_limit sets an upper alert limit for the value of ntc_ratio which corresponds to a low ( cold) temperature for the thermistor, and ntc_ratio_lo_alert_limit sets a lower alert limit for the value of ntc_ratio which corresponds to a high (hot) temperature for the thermistor. ltc 4015 4015fb
56 for more information www.linear.com/LTC4015 detailed register descriptions en_limit_alerts (sub-address 0x0d, bits 15:0, r/w) this register consists of individual limit alert enable bits. these bits enable monitoring and notification of limit excursions via smbalert and the limit_alerts (0 x36) register. see the section programmable alerts and interrupt controller for more information. en_meas_sys_valid_alert (sub-address 0x0d, bit 15, r/w) to achieve high measurement accuracy, the measurement system in the LTC4015 has a nominal warm up time of approximately 12 ms. setting this alert enable bit causes an smbalert when the measurement system indicates its results are valid. note that the LTC4015 switching charger will not operate until the measurement system warm up period has passed, regardless of the state of en_meas_sys_valid_alert. en_qcount_lo_alert (sub-address 0x0d, bit 13, r/w) setting this enable bit causes an smbalert when qcount has fallen below qcount_lo_alert_limit. qcount_ lo_alert is set to 1 by the LTC4015 if the alert occurs. en_qcount_hi_alert (sub-address 0x0d, bit 12, r/w) setting this enable bit causes an smbalert when qcount has exceeded qcount_ hi_ alert_ limit. qcount _ hi_ alert is set to 1 by the LTC4015 if the alert occurs. en _vbat_lo_alert (sub-address 0x0d, bit 11, r/w) setting this enable bit causes an smbalert when vbat has fallen below vbat_lo_alert_limit. vbat_lo_alert is set to 1 by the LTC4015 if the alert occurs. en_vbat_hi_alert (sub-address 0x0d, bit 10, r/w) setting this enable bit causes an smbalert when vbat has exceeded vbat_hi_alert_limit. vbat_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_vin_lo_alert (sub-address 0x0d, bit 9, r/w) setting this enable bit causes an smbalert when vin has fallen below vin_lo_alert_limit. vin_lo_alert is set to 1 by the LTC4015 if the alert occurs. en_vin_hi_alert (sub-address 0x0d, bit 8, r/w) setting this enable bit causes an smbalert when vin has exceeded vin_hi_alert_limit. vin_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_vsys_lo_alert (sub-address 0x0d, bit 7, r/w) setting this enable bit causes an smbalert when vsys has fallen below vsys_lo_alert_limit. vsys_lo_alert is set to 1 by the LTC4015 if the alert occurs. en_vsys_hi_alert (sub-address 0x0d, bit 6, r/w) setting this enable bit causes an smbalert when vsys has exceeded vsys_hi_alert_limit. vsys_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_iin_hi_alert (sub-address 0x0d, bit 5, r/w) setting this enable bit causes an smbalert when iin has exceeded iin_hi_alert_limit. iin_hi_alert is set to 1 by the LTC4015 if the alert occurs. ltc 4015 4015fb
57 for more information www.linear.com/LTC4015 detailed register descriptions en_ibat_lo_alert (sub-address 0x0d, bit 4, r/w) setting this enable bit causes an smbalert when ibat has fallen below ibat_lo_alert_limit. ibat_lo_alert is set to 1 by the LTC4015 if the alert occurs. en_die_temp_hi_alert (sub-address 0x0d, bit 3, r/w) setting this enable bit causes an smbalert when die_temp has exceeded die_temp_hi_alert_limit. die_ temp_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_bsr_hi_alert (sub-address 0x0d, bit 2, r/w) setting this enable bit causes an smbalert when bsr has exceeded bsr_hi_alert_limit. bsr_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_ntc_ratio_hi_alert (sub-address 0x0d, bit 1, r/w) setting this enable bit causes an smbalert when ntc_ratio has exceeded ntc_ratio_hi_alert_limit (cold battery). recall that the thermistor has a negative temperature coefficient so higher temperatures correspond to lower ntc_ratio readings and vice-versa. ntc_ratio_hi_alert is set to 1 by the LTC4015 if the alert occurs. en_ntc_ratio_lo_alert (sub-address 0x0d, bit 0, r/w) setting this enable bit causes an smbalert when ntc_ratio has fallen below ntc_ratio_lo_alert_limit (hot battery). recall that the thermistor has a negative temperature coefficient so higher temperatures correspond to lower ntc_ratio readings and vice-versa. ntc_ratio_lo_alert is set to 1 by the LTC4015 if the alert occurs. en_charger_state_alerts (sub-address 0x0e, bits 10:0, r/w) this register consists of individual charger state alert enable bits, which enable notification via smbalert based on the phase of a battery charge cycle. see the charger_ state (0 x37) register details and the sections battery charger algorithms and programmable alerts and interrupt controller for more information. en_equalize_charge_alert (sub-address 0x0e, bit 10, r/w) setting this enable bit causes an smbalert when the LTC4015 is in the equalize phase of a battery charge cycle (equalize_charge=1, applies to lead-acid chemistries only). en_absorb_charge_alert (sub-address 0x0e, bit 9, r/w) setting this enable bit causes an smbalert when the LTC4015 is in the absorb phase of a battery charge cycle (absorb_charge=1, applies to lifepo 4 and lead-acid chemistries only). en_charger_suspended_alert (sub-address 0x0e, bit 8, r/w) setting this enable bit causes an smbalert when the LTC4015 charger is suspended (charger_suspended=1). en _precharge_alert (sub-address 0x0e, bit 7, r/w) setting this enable bit causes an smbalert when the LTC4015 is in precondition charge phase of a battery charge cycle ( precharge=1) due to the battery being below the low battery threshold of 2.9v/cell ( applies to li-ion chem- istries only). en _cc_cv_charge_alert (sub-address 0x0e, bit 6, r/w) setting this enable bit causes an smbalert when the LTC4015 is in the cc-cv phase of a battery charge cycle (cc_cv_charge=1). ltc 4015 4015fb
58 for more information www.linear.com/LTC4015 detailed register descriptions en_ntc_pause_alert (sub-address 0x0e, bit 5, r/w) setting this enable bit causes an smbalert when the LTC4015 is in thermistor pause state ( ntc_pause=1) due to ntc_ratio out of range as set by the jeita_t1 and jeita_t6 values. see the section j.e.i.t.a. temperature qualified charging (applies to lithium chemistries only). en_timer_term_alert (sub-address 0x0e, bit 4, r/w) setting this enable bit causes an smbalert when the LTC4015 is in timer termination state ( timer_term=1) due to battery being at v charge for more than max_charge_time (applies to lithium chemistries only). en_c_over_x_term_alert (sub-address 0x0e, bit 3, r/w) setting this enable bit causes an smbalert when the LTC4015 is in c/x termination state ( c_over_x_term=1) due to ibat dropping below c_over_x_threshold (applies to lithium chemistries only). en_max_charge_time_fault_alert (sub-address 0x0e, bit 2, r/w) setting this enable bit causes an smbalert when the LTC4015 is in max charge time fault (max_charge_time_ fault = 1) due to max_charge_timer exceeding max_charge_time during a charge cycle (applies to lithium chemistries only). en_bat_missing_fault_alert (sub-address 0x0e, bit 1, r/w) setting this enable bit causes an smbalert if the LTC4015 is in battery missing fault state (bat_missing_fault=1) due to no batter y detected. en_bat_short_fault_alert (sub-address 0x0e, bit 0, r/w) setting this enable bit causes an smbalert if the LTC4015 is in shorted battery fault state ( bat_short_fault=1) be- cause the battery was determined to be shorted during the battery detection phase at the beginning of a charge cycle. en_charge_status_aler ts (sub-address 0x0f, bits 3:0, r/w) this register consists of individual charge status alert enable bits, which enable notification via smbalert based on the status of the battery charge current control circuitry. see the charge_status register details and the section programmable alerts and interrupt controller for more information. en_vin_uvcl_active_alert (sub-address 0x0f, bit 3, r/w) setting this enable bit causes an smbalert when the uvcl undervoltage current limit regulation loop of the LTC4015 is in control of the switching charger current delivery (vin_uvcl_active=1). en _iin_limit_active_alert (sub-address 0x0f, bit 2, r/w) setting this enable bit causes an smbalert when the input current regulation loop of the LTC4015 is in control of the switching charger current delivery (iin_limit_active=1). en_constant_current_alert (sub-address 0x0f, bit 1, r/w) setting this enable bit causes an smbalert when the battery charge current regulation loop of the LTC4015 is in control of the switching charger current delivery (constant_current=1). en_constant_voltage_alert (sub-address 0x0f, bit 0, r/w) setting this enable bit causes an smbalert when the battery voltage regulation loop of the LTC4015 is in control of the switching charger current delivery (constant_voltage=1). ltc 4015 4015fb
59 for more information www.linear.com/LTC4015 detailed register descriptions qcount_lo_alert_limit (sub-address 0x10, bits 15:0, r/w) qcount_hi_alert_limit (sub-address 0x11, bits 15:0, r/w) these 16- bit words set and lower and upper limits on qcount that can be used to trigger an smbalert when qcount falls below qcount_lo_alert_limit, or qcount exceeds qcount_hi_alert_limit. the values use the same format as qcount. qcount_prescale_factor (sub-address 0x12, bits 15:0, r/w) this 16-bit word along with r snsb is used to set the q lsb value of coulomb counter accumulator, qcount. q lsb = qcount_prescale_factor 8333.33 ?r snsb a ? s(coulombs) qcount (sub-address 0x13, bits 15:0, r/w) this 16- bit word reports the current value of coulomb counter accumulator, qcount. this register can be written to represent a known state of charge of the battery. q lsb = qcount_prescale_factor 8333.33 ?r snsb a ? s(coulombs) config_bits (sub-address 0x14, bits 8:0, r/w) this register consists of individual system configuration bits which control various features of the LTC4015. suspend_charger (sub-address 0x14, bit 8, r/w) setting this bit causes battery charging to be suspended, and forces charger_suspended=1. a new battery charge cycle can be forced by setting and then resetting suspend_charger. run_bsr (sub-address 0x14, bit 5, r/w) setting this bit causes a single battery series resistance ( bsr) measurement to be made by the LTC4015. once the series resistance measurement is complete, the LTC4015 resets the run_bsr bit to 0, and the result is reported as bsr. icharge_bsr is the value of ibat that was used in the bsr calculation. see the section battery series resistance measurement. force_meas_sys_on (sub-address 0x14, bit 4, r/w) setting this bit causes the a/d measurement system to operate at all times, including when input power is unavailable (vin_gt_vbat=0). this feature is disabled by default in order to reduce battery-only load current. setting this bit has the advantage of maintaining up-to-date system data, but will increase battery drain. when input power is absent, the measurement system can be sampled periodically to reduce quiescent current. see the measurement subsystem description for details. mppt_en_i2c (sub-address 0x14, bit 3, r/w) setting this bit causes the maximum power point tracking algorithm to run when the switching charger is active. the maximum power point algorithm uses the uvcl regulation loop to seek the optimum power point for resistive sources such as a solar panel. see the section maximum power point tracking for more information. the maximum power point algorithm can also be enabled by connecting the mppt pin to the 2p5v cc pin. the mppt_en_i2c bit is logically ored with the mppt pin. to disable mppt both the mppt_en_i2c bit and the mppt pin must be low. en_qcount (sub-address 0x14, bit 2, r/w) setting this bit enables the LTC4015 coulomb counter. this feature is disabled by default to reduce quiescent current. ltc 4015 4015fb
60 for more information www.linear.com/LTC4015 detailed register descriptions iin_limit_setting (sub-address 0x15, bits 5:0, r/w) these 6 bits control the target input current limit setting. the input current will be regulated to a maximum value given by (iin_limit_setting + 1) ? 500v/r snsi . vin_uvcl_setting (sub-address 0x16, bits 7:0, r/w) these 8 bits control the uvclfb regulation loop servo voltage. the uvclfb regulation voltage is given by (vin_uvcl_ setting + 1) ? 4.6875 mv. by default, this register is set to full-scale (0 xff), corresponding to 1.2 v at uvclfb pin. if enabled, the maximum power point tracking (mppt) algorithm directly manipulates vin_uvcl_setting. arm_ship_mode (sub-address 0x19, bits 15:0, r/w) setting this register to 0x534d ( ascii for sm) arms LTC4015s low power ship mode. the only allowed values for this register are 0 x0000 and 0 x534d, and once armed, ship mode cannot be disarmed ( writing arm_ship_mode=0 does not disarm ship mode). ship mode does not take effect until v in drops below approximately 1 v. see the section low power ship mode. charger setting register descriptions (sub-addresses 0x1a through 0x2e) registers which control the primary charging parameters, such as charge voltage and charge current are only writ- able when the chemn pins are configured for a programmable chemistry algorithm ( li-ion-prog, lifepo 4 -prog, or lead-acid-prog). if the chemn pins are configured for a fixed chemistry algorithm ( li-ion-fixed-4.2, li-ion-fixed-4.1, li-ion-fixed-4.0, lifepo 4 -fixed-3.6, lifepo 4 -fixed-3.8/3.6, or lead-acid-fixed) the LTC4015 ignores writes to these registers. see the section chemistry selection for more information about configuring the chemn pins. icharge_target (sub-address 0x1a, bits 4:0, fixed: r, programmable: r/w) this register controls the target charge current regulation servo level for lead-acid batteries or if en_jeita=0 for lithium chemistries. for lithium chemistries, if en_jeita =1 ( default) icharge_target is controlled by icharge_jeita_n (see the section jeita temperature controlled charging). the charge current regulation servo level is generally given by ( icharge_target + 1) 1mv/r snsb , except during li-ion precondition charge phase when the charge current regulation servo level is reduced by approximately a factor of 10 (rounded down to an increment of 1mv/r snsb ). vcharge_setting (sub-address 0x1b, bits 5:0, fixed: r, programmable: r/w) this register controls the charge voltage regulation servo level. the LTC4015 does not monitor or balance individual cells C the full battery stack voltage is divided by number of cells ( v/cell) for simplicity only. the 4015 is not a substitute for pack protection! for li-ion batteries, only the lower five bits (4:0) are active, and the charge voltage level is given by (vcharge_ setting/80.0 + 3.8125) v/cell. if en_jeita=1, vcharge_setting is controlled by vcharge_jeita_n ( see the section jeita temperature qualified charging). to maintain inherent over charge protection, the maximum li-ion charge voltage level is 4.2v/cell. for lifepo 4 batteries, only the lower five bits (4:0) are active, and the charge voltage level is given by (vcharge_ setting/80.0 + 3.4125) v/cell. if en_jeita=1, vcharge_setting is controlled by vcharge_jeita_n ( see the section jeita temperature qualified charging). to maintain inherent over-charge protection, the maximum lifepo 4 charge voltage level is 3.8v/cell. for lead-acid batteries, if en_lead_acid_temp_comp=1, the charge voltage level is given by (vcharge_setting/105.0 + 2.0) v/cell at 25 c when a thermistor with a value of 3490 k is used. see the section lead-acid temperature compensated charging for more information. if en_lead_acid_temp_comp=1, the value of vcharge_setting is limited to a maximum setting of 35, which corresponds to 2.333 v/cell. if en_lead_acid_temp_comp=0, the charge ltc 4015 4015fb
61 for more information www.linear.com/LTC4015 detailed register descriptions voltage level is given by ( vcharge_setting/105.0 + 2.0) v/cell, regardless of temperature. to maintain inherent over charge protection, the maximum lead-acid charge voltage level is 2.6 v/cell. vabsorb_delta (sub-address 0x2a, bits 5:0, fixed: r, programmable: r/w) this register controls the absorb adder voltage for lifepo 4 and lead-acid batteries in absorb charge phase. the absorb charge phase battery voltage servo level is based on the sum of the absorb adder voltage and the charge voltage level. for li-ion batteries, vabsorb_delta is ignored. for lifepo 4 batteries, only the lower five bits (4:0) are active, and the absorb voltage level is given by (vabsorb_delta + vcharge_setting )/80 + 3.4125 v/cell, limited to a maximum of 3.8 v/cell. setting vabsorb_delta=0 disables the absorb phase. see the section lifepo 4 absorb charge for more information. for lead-acid batteries, if en_lead_acid_temp_comp=1, the absorb voltage level is given by (vabsorb_delta + vcharge_setting)/105.0 + 2.0 v/cell at 25 c when a thermistor with a value of 3490 k is used. see the section lead-acid temperature compensated charging for more information. if en_lead_acid_temp_comp=0, the absorb voltage level is given by (vabsorb_delta + vcharge_setting)/105.0 + 2.0 v/cell, regardless of temperature. to maintain inherent over charge protection, the maximum lead-acid absorb voltage level is 2.6 v/cell. vequalize_delta (sub-address 0x2c, bits 5:0, fixed: r, programmable: r/w) these six bits control the equalize adder voltage for lead-acid batteries in equalize charge phase. the equalize charge phase batter y voltage servo level is based on the sum of the equalize adder voltage and the vcharge level. for lead-acid batteries, if en_lead_acid_temp_comp=1, the equalize voltage level is given by (vequalize_delta + vcharge_setting) / 105.0 + 2.0 v/cell at 25 c when a typical curve two thermistor is used. see the section lead-acid temperature compensated charging for more information. if en_lead_acid_temp_comp=0, the equalize voltage level is given by ((vequalize_delta + vcharge_setting)/105.0 + 2.0) v/cell, regardless of temperature. to maintain inherent over charge protection, the maximum lead-acid equalize voltage level is 2.6v/cell. for lithium chemistries, vequalize_delta is ignored. c_over_x_threshold (sub-address 0x1c, bits 15:0, fixed: r, programmable: r/w) this 16- bit word sets the ibat value used to qualify c/x detection for charge phase termination/transition. c_over_x_ threshold uses the same format as ibat, and the c/x current level is given by c_over_x_threshold/(r snsb ? 21845.0/0.032 v). the default value for c_over_x_threshold is 2184, which corresponds to 10% (3.2 mv) of a 32mv/ r snsb full-scale charge current. c/x detection is disabled if c_over_x_threshold is set to zero. for li-ion batteries, if en_c_over_x_term =1 (0 by default), c/x charge termination occurs after the battery reaches the charge voltage level and ibat drops below c_over_x_threshold. see the section c/x termination. for lifepo 4 batteries, if en_c_over_x_term =1 (0 by default), c/x charge termination occurs after the battery reaches vcharge level and ibat drops below c_ over _x_ threshold during cc- cv charge phase. see the section c/x termination. if the optional lifepo 4 absorb charge phase is employed and if c_over_x_threshold is set to a non-zero value, the absorb phase ends if the battery voltage reaches absorb level and ibat drops below c_over_x_threshold, and cc-cv phase begins. see the section lifepo 4 absorb charge. for lead-acid batteries, if c_over_x_threshold is non-zero, absorb charge phase ends after the battery voltage reaches absorb level and ibat drops below c_ over _x_ threshold, and the cc- cv charge phase continues indefinitely. ltc 4015 4015fb
62 for more information www.linear.com/LTC4015 detailed register descriptions max_cv_time (sub-address 0x1d, bits 15:0, fixed: r, programmable: r/w) for lithium chemistries, this 16- bit word sets the termination time limit at one second per count. if the charger is in the cv state for max_cv_time seconds, timer termination occurs. the actual timer value is reported in cv_timer. see the section timer termination for more information. the default setting is four hours (14,400) for li- ion batteries and one hour (3,600) for lifepo 4 batteries. for lead-acid batteries, max_cv_time is ignored. max_absorb_time (sub-address 0x2b, bits 15:0, fixed: r, programmable: r/w) for lifepo 4 and lead-acid batteries, this 16- bit word sets an upper limit on the time ( at one second per count) that the battery can be in the absorb charge phase. the actual timer value is reported in absorb_timer. see the sections lifepo 4 absorb charge and lead-acid absorb charge. for li-ion batteries, max_absorb_time is ignored. equalize_time (sub-address 0x2d, bits 15:0, fixed: r, programmable: r/w) for lead -acid batteries, this 16- bit word sets the time ( at one second per count) for the equalization charge phase. for lead-acid batteries , the default setting is 3600 seconds. see the section lead-acid equalization charge. for lithium chemistries, equalize_time is ignored. max_charge_time (sub-address 0x1e, bits 15:0, fixed: r, programmable: r/w) for lithium chemistries, this 16- bit word sets the max_charge_time fault detection time at one second per count. the default setting is 18.2 hours (65535). if the max_charge_timer exceeds max_charge_time during charging, a max charge time fault occurs. see the section max charge time fault for more information. for lead-acid batteries, max_charge_time is ignored. lifep04_recharge_threshold (sub-address 0x2e, bits 15:0, fixed: r, programmable: r/w) in lifepo 4 programmable mode only, this 16 bit two's complement word sets the recharge threshold, where the recharge threshold/cell = [lifepo4_recharge_threshold] ? 192.264v. default is 0x4410 which is 3.35v/cell. jeita_tn (sub-address 0x1f through 0x24, bits 15:0, fixed: r, programmable: r/w) (n = 1,2,3,4,5,6) for lithium chemistries, these six 16- bit words set the jeita temperature region break points t1 C t6, and have the same format as ntc_ratio. the temperatures are based on the thermistor reading from the measurement system. recall that the thermistor has a negative temperature coefficient so jeita_t1, representing colder temperatures, will have the highest value and jeita_t6, representing warmer temperatures, will have the lowest value. see the section jeita temperature qualified charging. jeita_tn are ignored for lead-acid batteries or if en_jeita=0. programming of jeita values region 1 region 2 region 3 region 4 region 5 region 6 region 7 [jeita_t1] [jeita_t2] [jeita_t3 ] [jeita_t4] [jeita_t5] [jeita_t6] charger off icharge _jeita_2 icharge_jeita_3 icharge_jeita_4 icharge_jeita_5 icharge_jeita_6 charger off vcharge_jeita_2 vcharge_jeita_3 vcharge_jeita_4 vcharge_jeita_5 vcharge_jeita_6 vcharge_jeita_6_5 (sub-address 0x25, bits 9:0, fixed: r, programmable: r/w), vcharge_jeita_4_3_2 (sub-address 0x26, bits 14:0, fixed: r, programmable: r/w) for lithium chemistries, these two registers contain the charge voltage settings to be used in the jeita voltage vs temperature profile. vcharge _ jeita_6_5 contains two bit packed values, vcharge _ jeita_6 (bits 9:5) and vcharge_ jeita_5 ltc 4015 4015fb
63 for more information www.linear.com/LTC4015 detailed register descriptions (bits 4:0). vcharge_jeita_4_3_2 contains three bit packed values, vcharge_jeita_4 (bits 14:10), vcharge_jeita_3 (bits 9:5), and vcharge_jeita_2 (bits 4:0). these registers are ignored for lead-acid batteries or if en_jeita=0. vcharge_jeita_n (n = 2,3,4,5,6) these five 5- bit values set the vcharge_setting values to be used in each of the jeita voltage vs temperature regions. there are no defined charge voltages for regions 1 and 7 because battery charging is paused in these regions. see the jeita temperature qualified charging section. programming of jeita values region 1 region 2 region 3 region 4 region 5 region 6 region 7 [jeita_t1] [jeita_t2] [jeita_t3 ] [jeita_t4] [jeita_t5] [jeita_t6] charger off icharge _jeita_2 icharge_jeita_3 icharge_jeita_4 icharge_jeita_5 icharge_jeita_6 charger off vcharge_jeita_2 vcharge_jeita_3 vcharge_jeita_4 vcharge_jeita_5 vcharge_jeita_6 icharge_jeita_6_5 (sub-address 0x27, bits 9:0, fixed: r, programmable: r/w), icharge_jeita_4_3_2 (sub-address 0x28, bits 14:0, fixed: r, programmable: r/w) for lithium chemistries, these two registers contain the charge current settings to be used in the jeita current vs temperature profile. icharge_jeita_6_5 contains two bit packed values, icharge_jeita _6 (bits 9:5) and icharge_jeita_5 (bits 4:0). icharge_jeita_4_3_2 contains three bit packed values, icharge_jeita_4 (bits 14:10), icharge_jeita_3 (bits 9:5), and icharge_jeita_2 (bits 4:0). these registers are ignored for lead-acid batteries or if en_jeita=0. icharge_jeita_n (n = 2,3,4,5,6) these five 5- bit values set the icharge_target values to be used in each of the jeita current vs temperature regions. there are no defined charge currents for regions 1 and 7 because battery charging is paused in these regions. see the jeita temperature qualified charging section. programming of jeita values region 1 region 2 region 3 region 4 region 5 region 6 region 7 [jeita_t1] [jeita_t2] [jeita_t3 ] [jeita_t4] [jeita_t5] [jeita_t6] charger off icharge _jeita_2 icharge_jeita_3 icharge_jeita_4 icharge_jeita_5 icharge_jeita_6 charger off vcharge_jeita_2 vcharge_jeita_3 vcharge_jeita_4 vcharge_jeita_5 vcharge_jeita_6 charger_config_bits (sub-address 0x29, bits 2:0, fixed: r, programmable: r/w) this register consists of individual battery charger configuration bits which enable specific battery charger functions. en_c_over_x_term (sub-address 0x29, bit 2, fixed: r, programmable: r/w) for lithium chemistries, setting this bit enables c/x charge termination, in conjunction with c_over_x_threshold. for lead-acid batteries, en_c_over_x_term is ignored. default is 0. en_lead_acid_temp_comp (sub-address 0x29, bit 1, fixed: r, programmable: r/w) for lead-acid batteries, setting this bit enables temperature compensated charge voltage levels as detailed in the lead-acid temperature compensated charging section. default is 1 for lead-acid batteries. for lithium chemistries, en_lead_acid_temp_comp is ignored. en_jeita (sub-address 0x29, bit 0, fixed: r, programmable: r/w) for lithium chemistries, setting this bit enables the jeita temperature qualified algorithm as detailed in the jeita temperature qualified charging section. the charging parameters are set by jeita_tn, vcharge_jeita_n, and icharge_jeita _n. default is 1 for lithium chemistries. for lead-acid batteries, en_jeita is ignored. ltc 4015 4015fb
64 for more information www.linear.com/LTC4015 detailed register descriptions readouts, status, and alerts (sub-addresses 0x34 through 0x46) max_charge_timer (sub-address 0x30, bits 15:0, r) for lithium chemistries, this 16- bit word indicates the time ( in seconds) that the battery has been charging. see the max_charge_time register description and the section maximum charge time for more information. for lead-acid batteries, max_charge_timer is not used. cv_timer (sub-address 0x31, bits 10:0, r) for lithium chemistries, this 16- bit word indicates the time ( in seconds) that the battery has been in constant-voltage regulation. see the max_cv_time register description and the section timer termination for more information. for lead-acid batteries, cv_timer is not used. absorb_timer (sub-address 0x32, bits 10:0, r) for lifepo 4 and lead-acid batteries, this 16- bit word indicates the time ( in seconds) that the battery has been in absorb phase. see the max_absorb_time register description and the sections lifepo 4 absorb charge and lead-acid absorb charge for more information. for li-ion batteries, absorb_timer is not used. equalize_timer (sub-address 0x33, bits 15:0, fixed: r, programmable: r/w) for lead -acid batteries, this 16- bit word indicates the time ( in seconds) that the battery has been in equalization charge phase. see the equalize_time register description and the section lead-acid equalization charge. for lithium chemistries, equalize_timer is not used. charger_state (sub-address 0x34, bits 10:0, r) this register consists of individual battery charger state indicator bits. individual bits are mutually exclusive ( a maximum of one bit is asserted at any given time). see the section battery charger algorithms for more information regarding the charger states. equalize_charge (sub-address 0x34, bit 10, r) this bit indicates that the LTC4015 is in the equalize phase of a battery charge cycle ( applies to lead-acid chemis- tries only). absorb _charge (sub-address 0x34, bit 9, r) this bit indicates that the LTC4015 is in the absorb phase of a battery charge cycle ( applies to lifepo 4 and lead- acid chemistries only). charger_suspended (sub-address 0x34, bit 8, r) this bit indicates that the LTC4015 charger is suspended, due to any of the following conditions occurring : ( a) the input voltage on the v in pin falls below or within 100 mv of the batsens pin voltage, ( b) suspend_charger is writ- ten to 1 via the serial port, or ( c) a system fault condition occurs (v in overvoltage , 2p5v cc undervoltage, intv cc undervoltage, drv cc undervoltage, thermal shutdown, missing r t resistor, or invalid combination of cells pins). precharge (sub-address 0x34, bit 7, r) this bit indicates that the LTC4015 is in the precondition charge phase of a battery charge cycle due to the battery being below the low batter y threshold of 2.9v/cell (applies to li-ion chemistries only). cc_cv_charge (sub-address 0x34, bit 6, r) this bit indicates that the LTC4015 is in the cc-cv phase of a battery charge cycle. ltc 4015 4015fb
65 for more information www.linear.com/LTC4015 detailed register descriptions ntc_pause (sub-address 0x34, bit 5, r) this bit indicates that the LTC4015 is in thermistor pause state due to ntc_ratio out of range as set by the jeita_tn values. see the section jeit a temperature qualified charging (applies to lithium chemistries only). timer_term (sub-address 0x34, bit 4, r) this bit indicates that the LTC4015 is in timer termination state due to battery being at the vcharge voltage for more than max_cv_time (applies to lithium chemistries only). c_over_x_term (sub-address 0x34, bit 3, r) this bit indicates that the LTC4015 is in c/x termination state due to ibat dropping below c_over_x_threshold (applies to lithium chemistries only). max_charge_time_fault (sub-address 0x34, bit 2, r) this bit indicates that the LTC4015 is in max charge time fault state due to max_charge_timer exceeding max_charge_time during a charge cycle (applies to lithium chemistries only). bat_missing_fault (sub-address 0x34, bit 1, r) this bit indicates that the LTC4015 is in battery missing fault state due to no battery detected. bat _short_fault (sub-address 0x34, bit 0, r) this bit indicates that the LTC4015 is in battery short fault state due to a shorted battery detected. charge _st atus (sub-address 0x35, bits 3:0, r) this register consists of individual status bits which indicate status of the battery charge current control circuitry. individual bits are mutually exclusive (a maximum of one bit is asserted at any given time). vin_uvcl_active (sub-address 0x35, bit 3, r) this bit indicates that the uvclfb pin of the undervoltage current limit loop of the LTC4015 is in control of the switching charger current delivery based on vin_uvcl_setting. iin_limit_active (sub-address 0x35, bit 2, r) this bit indicates that the input current regulation loop of the LTC4015 is in control of the switching charger current delivery based on iin_limit_set ting. constant_current (sub-address 0x35, bit 1, r) this bit indicates that the battery charge current regulation loop of the LTC4015 is in control of the switching charger current delivery based on icharge_dac. constant_voltage (sub-address 0x35, bit 0, r) this bit indicates that the battery voltage regulation loop of the LTC4015 is in control of the switching charger current delivery based on vcharge_dac. limit _aler ts (sub-address 0x36, bits 15:0, r/clear) this register consists of individual alert bits which can optionally indicate that limit excursions have caused an smbalert to occur. the LTC4015 checks for new limits excursions at the end of every a/d measurement system cycle ( approximately 6.5ms), and limit_alerts is updated accordingly. individual alert bits are enabled by en_limit_alerts. once asserted, alert bits remain high until disabled or cleared. writing a 0 to any bit clears that alert. if an enabled alert is cleared and the alerting condition remains, a new alert is triggered immediately. when a new alert occurs, the LTC4015 pulls down the smbalert pin and holds it low until it completes a response to an alert response algorithm ltc 4015 4015fb
66 for more information www.linear.com/LTC4015 detailed register descriptions (ara). see the section programmable alerts and interrupt controller for more information regarding the smbalert and ara functions. meas_sys_valid_alert (sub-address 0x36, bit 15, r/clear) to achieve high measurement accuracy, the measurement system in the LTC4015 has a typical warm up time of approximately 12 ms. if en_meas_sys_valid_alert=1, the meas_sys_valid_alert bit indicates that an smbalert has occurred because the warm-up period has passed and the a/d measurement system results are valid. this can be particularly useful in battery only mode for periodic sampling of the measurement system; see force_meas_sys_on for more information. qcount_lo_alert (sub-address 0x36, bit 13, r/clear) if en _qcount_lo_alert=1, this bit indicates that an smbalert has occurred because qcount has fallen below qcount_lo_alert_limit. qcount_hi_alert (sub-address 0x36, bit 12, r/clear) if en _qcount_hi_alert=1, this bit indicates that an smbalert has occurred because qcount has exceeded qcount_hi_alert_limit. vbat_lo_alert (sub-address 0x36, bit 11, r/clear) if en _vbat_lo_alert =1, this bit indicates that an smbalert has occurred because vbat has fallen below vbat_ lo_alert_limit. vbat_hi_alert (sub-address 0x36, bit 10, r/clear) if en _vbat_hi_alert =1, this bit indicates that an smbalert has occurred because vbat has exceeded vbat_hi_ alert_limit. vin_lo_alert (sub-address 0x36, bit 9, r/clear) if en _vin_lo_alert =1, this bit indicates that an smbalert has occurred because vin has fallen below vin_lo_ alert_limit. vin_hi_alert (sub-address 0x36, bit 8, r/clear) if en _vin_hi_alert =1, this bit indicates that an smbalert has occurred because vin has exceeded vin_hi_alert_ limit. vsys_lo_alert (sub-address 0x36, bit 7, r/clear) if en _vsys_lo_alert =1, this bit indicates that an smbalert has occurred because vsys has fallen below vsys_ lo_alert_limit. vsys_hi_alert (sub-address 0x36, bit 6, r/clear) if en _vsys_hi_alert =1, this bit indicates that an smbalert has occurred because vsys has exceeded vsys_hi_ alert_limit. iin_hi_alert (sub-address 0x36, bit 5, r/clear) if en _ iin _ hi_ alert =1, this bit indicates that an smbalert has occurred because iin has exceeded iin_ hi_ alert_ limit. ibat_lo_alert (sub-address 0x36, bit 4, r/clear) if en_ibat_lo_alert =1, this bit indicates that an smbalert has occurred because ibat has fallen below ibat_lo_ alert_limit. ltc 4015 4015fb
67 for more information www.linear.com/LTC4015 detailed register descriptions die_temp_hi_alert (sub-address 0x36, bit 3, r/clear) if en _die_temp_hi_alert =1, this bit indicates that an smbalert has occurred because die_temp has exceeded die_temp_hi_alert_limit. bsr_hi_alert (sub-address 0x36, bit 2, r/clear) if en _bsr_hi_alert =1, this bit indicates that an smbalert has occurred because bsr has exceeded bsr_hi_ alert_limit. ntc_ratio_hi_alert (sub-address 0x36, bit 1, r/clear) if en _ntc_ratio_hi_alert =1, this bit indicates that an smbalert has occurred because ntc_ratio has exceeded ntc_ratio_hi_alert_limit (cold batter y). ntc_ratio_lo_alert (sub-address 0x36, bit 0, r/clear) if en _ntc_ratio_hi_alert =1, this bit indicates that an smbalert has occurred because ntc_ratio has fallen below ntc_ratio_lo_alert_limit (hot battery) charger_state_alerts (sub-address 0x37, bits 10:0, r/clear) this register consists of individual battery charger state alert bits. individual alert bits will be asserted if the individual alert has been enabled and the transition into that state occurs. once asserted, alert bits remain high until disabled or cleared. writing a 0 to any bit clears that alert . if an enabled alert is cleared and the alerting condition remains, a new alert is triggered immediately. when a new alert occurs, the LTC4015 pulls down the smbalert pin and holds it low until an alert response algorithm ( ara) is completed. see the section programmable alerts and interrupt controller for more information regarding the smbalert and ara functions. equalize_charge_alert (sub-address 0x37, bit 10, r/clear) if en _equalize_charge_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of equalize_ charge (applies to lead-acid chemistries only). absorb_charge_alert (sub-address 0x37, bit 9, r/clear) if en _absorb_charge_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of absorb_ charge (applies to lifepo 4 and lead-acid chemistries only). charger_suspended_alert (sub-address 0x37, bit 8, r/clear) if en _charger_suspended_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of charger_suspended. precharge_alert (sub-address 0x37, bit 7, r/clear) if en_precharge _alert=1, this bit indicates that an smbalert has occurred due to the occurrence of precharge. cc _cv_charge_alert (sub-address 0x37, bit 6, r/clear) if en_ cc _ cv _ charge _ alert=1, this bit indicates that an smbalert has occurred due to the occurrence of cc_ cv_ charge. ntc_pause_alert (sub-address 0x37, bit 5, r/clear) if en_ntc_pause_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of ntc_pause. timer _term_alert (sub-address 0x37, bit 4, r/clear) if en _timer_term_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of timer_term. c_over_x_term_alert (sub-address 0x37, bit 3, r/clear) if en _ c_ over _x_ term_ alert=1, this bit indicates that an smbalert has occurred due to the occurrence of c_ over _x_ term. ltc 4015 4015fb
68 for more information www.linear.com/LTC4015 detailed register descriptions max_charge_time_fault_alert (sub-address 0x37, bit 2, r/clear) if en _max_charge_time_fault_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of a max_charge_time_fault. bat_missing_fault_alert (sub-address 0x37, bit 1, r/clear) if en _bat_missing_fault_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of bat_missing_fault. bat_short_fault_alert (sub-address 0x37, bit 0, r/clear) if en _bat_short_fault_alert=1, this bit indicates that an smbalert has occurred due to the occurrence of bat_ short_fault. charge_status_aler ts (sub-address 0x38, bits 3:0, r/clear) this register consists of individual battery charger charge status alert bits. individual alert bits will be asserted if the individual alert has been enabled and the transition into that state occurs. once asserted, alert bits remain high until disabled or cleared. writing a 0 to any bit clears that alert. if an enabled alert is cleared and the alerting condition remains, a new alert is triggered immediately. when a new alert occurs, the LTC4015 pulls down the smbalert pin and holds it low until an alert response algorithm ( ara) is completed. see the s ection programmable alerts and interrupt controller for more information regarding the smbalert and ara functions. vin_uvcl_active_alert (sub-address 0x38, bit 3, r/clear) if en _vin_uvcl_active_alert=1, this bit indicates that an smbalert has occurred because the uvcl undervolt- age current limit regulation loop of the LTC4015 has taken control of the switching regulator charger delivery (vin_uvcl_active=1). iin _limit_active_alert (sub-address 0x38, bit 2, r/clear) if en _iin_limit_active_alert=1, this bit indicates that an smbalert has occurred because the input current regulation loop of the LTC4015 has taken control of the switching regulator charger delivery (iin_limit_active=1). constant_current_alert (sub-address 0x38, bit 1, r/clear) if en _constant_current_alert=1, this bit indicates that an smbalert has occurred because the battery charge current regulation loop of the LTC4015 has taken control of the switching charger current delivery (constant_current=1). constant_voltage_alert (sub-address 0x38, bit 0, r/clear) if en _constant_voltage_alert=1, this bit indicates that an smbalert has occurred because the battery voltage regulation loop of the LTC4015 has taken control of the switching charger current delivery (constant_voltage=1). system _st atus (sub-address 0x39, bits 13:0, r) this register consists of individual real-time status bits which indicate various system conditions. charger_enabled (sub-address 0x39, bit 13, r) this bit indicates that the LTC4015 is actively charging a battery. mppt _en_pin (sub-address 0x39, bit 11, r) this bit indicates that the external mppt pin is detected as being high and maximum power point tracking is enabled. equalize_req (sub-address 0x39, bit 10, r) this bit indicates that a rising edge has been detected at the eq pin and a lead-acid equalization charge is running or is queued to run. see lead-acid equalization charge. ltc 4015 4015fb
69 for more information www.linear.com/LTC4015 detailed register descriptions drvcc_good (sub-address 0x39, bit 9, r) this bit indicates that the drv cc pin voltage is above the drv cc undervoltage lockout level (4.3v typical). cell_count_error (sub-address 0x39, bit 8, r) this bit indicates that an invalid combination of cells pin settings have been detected. ok _to_charge (sub-address 0x39, bit 6, r) this bit indicates that all system conditions are met to allow battery charging operation. no _rt (sub-address 0x39, bit 5, r) this bit indicates that no frequency setting resistor is detected on the rt pin. the rt pin impedance detection circuit will typically indicate a missing r t resistor for values above 1.4m. thermal_shutdown (sub-address 0x39, bit 4, r) this bit indicates that the LTC4015 is in thermal shutdown protection due to an excessively high die temperature (typically 160c and above). vin_ovlo (sub-address 0x39, bit 3, r) this bit indicates that the LTC4015 is in input voltage shutdown protection due to an input voltage above its protec- tion shutdown threshold of approximately 38.6v (typical). vin _gt_vbat (sub-address 0x39, bit 2, r) this bit indicates that the v in pin input voltage is sufficiently above the batsens battery voltage to allow charging operation (typically +200mv). intvcc_gt_4p3v (sub-address 0x39, bit 1, r) this bit indicates that the intv cc voltage is above the switching charger undervoltage lockout threshold value of 4.3v (typical). intvcc_gt2p8v (sub-address 0x39, bit 0, r) this bit indicates that the intv cc pin voltage is above the measurement system undervoltage lockout threshold value of 2.8v (typical). vbat (sub-address 0x3a, bits 15:0, r) this 16-bit twos complement word indicates the a/d measurement result for the batsens pin. v batsens /cellcount = [vbat] ? 192.264v for lithium chemistries. v batsens /cellcount = [vbat] ? 128.176v for lead-acid. vin (sub-address 0x3b, bits 15:0, r) this 16- bit two s complement word indicates the a/d measurement result for the v in pin voltage divided by 30. input voltage, v vin = [vin] ? 1.648mv vsys (sub-address 0x3c, bits 15:0, r) this 16- bit two s complement word indicates the a/d measurement result for the sys pin voltage divided by 30. system voltage, v sys = [vsys] ? 1.648mv ibat (sub-address 0x3d, bits 15:0, r) this 16- bit word indicates the a/d measurement of 37.5 ? (v csp C v csn ) at the csp, csn pins. negative values are represented in twos complement notation and indicate current flowing out of ( discharging) the battery. battery current = [ibat] ? 1.46487v/r snsb ltc 4015 4015fb
70 for more information www.linear.com/LTC4015 detailed register descriptions iin (sub-address 0x3e, bits 15:0, r) this 16- bit word indicates the a/d measurement of 37.5 ? (v clp C v cln ) at the clp, cln pins. input current = [iin] ? 1.46487v/r snsi die_temp (sub-address 0x3f, bits 15:0, r) this 16- bit two s complement word indicates the a/d measurement result for LTC4015 die temperature. LTC4015 temperature = (die_temp C 12010)/45.6c ntc_ratio (sub-address 0x40, bits 15:0, r) this 16- bit twos complement word indicates the a/d measurement result for r ntc /(r ntc + r ntcbias ). the thermistor value can be determined by the expression r ntc = r ntcbias ? ntc_ratio /(21,845.0 C ntc_ratio). recall that the thermistor has a negative temperature coefficient so higher temperatures correspond to lower ntc_ratio readings and vice-versa. bsr (sub-address 0x41, bits 15:0, r) this 16- bit word indicates the calculated per cell battery series resistance. the battery series resistance is proportional to the battery charge current setting resistor, r snsb , and can be computed in from [bsr/500] ? r snsb for lithium chemistries, or [bsr/750] ? r snsb for lead-acid chemistries. multiply this value by the total number of cells to calculate total battery series resistance. icharge_bsr is the value of ibat used in the bsr calculation. jeita _ region (sub-address 0x42, bits 2:0, r) for lithium chemistries, this register indicates the jeita battery temperature region as determined by the a/d measurement result ntc_ratio and the values of the jeita_tn registers. recall that the thermistor has a negative temperature coefficient so higher temperatures make lower ntc_ratio readings and vice-versa. see the section jeita temperature qualified charging for a diagram of the temperature regions. chem_and_cells (sub-address 0x43, bits 11:0, r) this register indicates the state of the chemn and cellsn pins. see the sections chemistry selection and cells selec- tion for more information on defining the pin states. chem (sub-address 0x43, bits 11:8, r) these four bits indicate the chemistry algorithm set by the chemn pins, as shown in the following table. for ad- ditional safety , these bits can be checked during test and/or by the application software to ensure that LTC4015 is connected properly on the circuit board. chem: chem1,chem0: chemistry algorithm: 0x0 l, l li-ion programmable 0x1 h, h li-ion fixed 4.2v/cell 0x2 l, z li-ion fixed 4.1v/cell 0x3 z, l li-ion fixed 4.0v/cell 0x4 l, h lifepo 4 programmable 0x5 h, z lifepo 4 fixed fast charge 0x6 z, h lifepo 4 fixed 3.6v/cell 0x7 z, z lead-acid fixed 0x8 h, l lead-acid programmable cells (sub-address 0x43, bits 3:0, r) these four bits indicate the battery cell count set by the cellsn pins. for additional safety, these bits can be checked during test and/ or by the application software to ensure that LTC4015 is connected properly on the circuit board. ltc 4015 4015fb
71 for more information www.linear.com/LTC4015 icharge_dac (sub-address 0x44, bits 4:0, r) this register represents the actual charge current setting applied to the charge current reference dac. icharge_dac is ramped up/down to implement digital soft-start/stop. the LTC4015 sets the value of icharge_dac based on battery chemistry, charger state ( charger_state), thermistor reading ( ntc_ratio), and charger settings including icharge_target, ijeita_n, and tjeita_n. recall that the charge current is regulated by controlling the voltage across an external current sense resistor r snsb . the servo voltage is given by (icharge_dac + 1) ? 1 mv. the charge current servo level is thus given by (icharge_dac + 1) ? 1mv/r snsb . vcharge_dac (sub-address 0x45, bits 5:0, r) this register represents the actual target battery voltage setting applied to the charge voltage reference dac. the LTC4015 sets the value of vcharge_dac based on battery chemistry, charger state ( charger_state), thermistor reading ( ntc_ratio), and charger settings including vcharge_setting, vjeita_n, tjeita_n, vabsorb_delta, vequalize_delta,en_jeita, and en_lead_acid_temp_comp. see also jeita temperature qualified charging and lead-acid temperature compensated charging. iin_limit_dac (sub-address 0x46, bits 5:0, r) this register represents the actual input current limit setting applied to the input current limit reference dac. this register follows iin_limit_set ting. vbat_filt (sub-address 0x47, bits 15:0, r) digitally filtered twos complement adc measurement result for battery voltage. icharge _bsr (sub-address 0x48, bits 15:0, r) this 16-bit two's complement word is the value of ibat (0x3d) used in calculating bsr. telemetry _v alid (sub-address 0x4a, bit 0, r) this bit being set to 1 indicates the output of the LTC4015's telemetry system is valid. detailed register descriptions number of cells cells 2 cells1 cells0 invalid l l l 1 l l h 2 l h l 3 l h h 4 l l z 5 l z l 6 l h z 7 l z h 8 l z z 9 h l l invalid h l h invalid h h l 12* h h h *lead-acid only ltc 4015 4015fb
72 for more information www.linear.com/LTC4015 typical applications application circuit 1: li-ion battery charger, 2 = cell, 8a (typical performance characteristics) LTC4015 v in uvclfb controller intv cc v in 4.5v to 35v smbalert dv cc scl sda 10f 10k 1% 64.9k 1% 10k cells0 cells1 cells2 chem0 chem1 ccrefp ccrefm sgnd 100nf r ccref rt v c infet clp r snsi m3 1nf cln sys sysm5 4015 ta02 outfet system intv cc d1 m2 m4 m1 l1 10h drv cc boost tg sw bg cspm5 csp csn r snsb r ntcbias batsens ntcbias ntc eq mppt 1f 330nf 100nf 10f 10f 10f c1 0.47f 330nf 1nf r t 10nf (paddle) gnd r t : 95.3k 1% r ccref : 301k, 0.1%, 25ppm/c, susumu, rg1608p-3013-b-ts r snsi : 3m, susumu, krl3216t4-m-r003-f r snsb : 4m, susumu, krl3216t4-m-r004-f r ntcbias : 10k 1% r ntc : vishay ntcs0402e3103flt l1: 10h, coil craft xal8080_103me or wrth elektronik 7443321000 m1, m2: fairchild fdmc8030 (dual) m3: fairchild fdmc8327l m4: vishay si7611dn d1: diodes inc 1n4448hlp c1: 120f 40v, 40hvh120m 2p5v cc 10f r ntc battery pack t 10f 100pf 2.2nf 200 220nf 2.2f ltc 4015 4015fb
73 for more information www.linear.com/LTC4015 typical applications solar lead-acid battery charger, 6-cell 10.7a LTC4015 v in uvclfb controller intv cc v in solar panel smbalert dv cc scl sda 10f 10k 2.2nf 294k 1% 10k 1% cells0 cells1 cells2 chem0 chem1 ccrefp ccrefm 100nf r ccref rt v c infet clp r snsi m3 1nf cln sys sysm5 4015 ta03 outfet system intv cc d1 l1, 10h drv cc boost tg sw bg 2p5v cc cspm5 csp csn r snsb r ntcbias batsens ntcbias ntc eq mppt 1f 330nf 100nf 10f 10f m4 m2 m1 10f c1 c b 0.47f 2.2f 330nf 1nf r t 10nf (paddle) gnd r t : 95.3k 1% r ccref : 301k, 0.1%, 25ppm/c, susumu rg1608p-3013-b-t5 r snsi : 3m, vishay wsk06123l000fea (10.7a input current limit) r snsb : 3m, vishay wsk06123l000fea r ntcbias : 10k 1% r ntc : vishay ntcs0402e3103flt l1: 10h, coil craft xal1010_103me or wrth elektronik 7443321000 m1, m2: fairchild fdmc8030 (dual) m3: fairchild fdmc8327l m4: vishay si7611dn d1: diodes inc 1n4448hlp c1: 120f 40v, 40hvh120m 10f 10f r ntc battery pack t 100pf 200 220nf sgnd ltc 4015 4015fb
74 for more information www.linear.com/LTC4015 package description please refer to http://www .linear.com/product/LTC4015#packaging for the most recent package drawings. 5.00 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 0.10 0.75 0.05 r = 0.125 typ r = 0.10 typ 0.25 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 0.10 0.70 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 0.05 5.50 0.05 5.15 0.05 6.10 0.05 7.50 0.05 0.25 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 45 chamfer uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c) ltc 4015 4015fb
75 for more information www.linear.com/LTC4015 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 02/16 add a bullet in the data sheet conventions section. add range to v in and v bat in the parameter section. add text to note 11. add text to ntc (pin 11). add text to cells selection section. add text to end of 2nd paragraph on the left. edit last paragraph on the left. add text to the 1st paragraph in the LTC4015 charge algorithm overview section. add (per cell) to the bottom table. edit irms equation. add text to 4th and 5th paragraph on the right. add text to the mppt_en_i2c section. add text to 1st paragraph of vcharge_setting section. edit schematic in typical applications section. add ltc3300-1, ltc3305 and delete lt3651 and ltc4012 in related parts section. 3 4 9 13 24 27 34 35 44 46 61 62 76 b 04/17 update typical application schematic. change v sys = 35v. modify note 4. modify uvclfb (pin 8) section. correct chemo to (pin 36). update block diagram. update i 2 c timing diagram update table 7. modify maximum charge time section. update li-ion lifepo4 section. update table under operation section. update figure 8 and lead-acid charging parameters table. update figure 9. modify equation kqc = 8333.33hz/v. modify coulomb counter applications section. modify uvclfb resistor divider selection section. update t ypical applications schematics. 1 7 9 13 14 15 16 26 30 32 34 35 38 39 39 45, 46 72, 73 ltc 4015 4015fb
76 for more information www.linear.com/LTC4015 ? linear technology corporation 2015 lt 0417 rev b ? printed in usa www.linear.com/LTC4015 related parts typical application part number description comments lt3652/lt3652hv power tracking 2a buck battery charger input supply voltage regulation loop for peak power tracking in (mppt) solar applications, standalone, 4.95v v in 32v (40v abs max), 1mhz timer or c/10 termination, 3mm 3mm dfn-12 package and msop-12 packages, lt3652hv version up to v in = 34v ltc4020 55v buck-boost multi-chemistry battery charger constant-current/constant-voltage buck-boost switching controller regulator charger, 5mm 7mm qfn-38 package ltc4121/ ltc4121-4.2 multi-chemistr y buck battery charger constant-current/constant-voltage 400ma monolithic buck switching regulator charger, 4.4v v in 40v, 3mm 3mm qfn-16 package ltc4155 dual input power manager/3.5a li-ion battery charger high efficiency, monolithic switching regulator, 4mm 5mm qfn-28 package ltc3300-1 high efficiency bidirectional multicell battery balancer bidirectional synchronous flyback balancing of up to six li-ion or lifepo 4 cells in series. up to 10a balancing current (set by external components). bidirectional architecture minimizes balancing time and power dissipation. up to 92% charge transfer efficiency. 7mm 7mm qfn-48 and 7mm 7mm lqfp-48 packages ltc3305 lead-acid battery balancer single ic balances up to four 12v lead-acid batteries in series. stand alone operation requires no external p or control circuitry. thermally enhanced tssop-36 package solar lead-acid battery charger, 6-cell 10.7a, system fed from battery LTC4015 v in uvclfb controller intv cc v in solar panel smbalert dv cc scl sda 10f 10k 2.2nf 294k 1% 10k 1% cells0 cells1 cells2 chem0 chem1 ccrefp ccrefm 100nf r ccref rt v c infet clp r snsi m3 1nf cln sys sysm5 4015 ta04 outfet system intv cc d1 l1, 10h drv cc boost tg sw bg 2p5v cc cspm5 csp csn r snsb r ntcbias batsens ntcbias ntc eq mppt 1f 330nf 100nf 10f 10f m4 m2 m1 10f c1 c b 0.47f 2.2f 330nf 1nf r t 10nf (paddle) gnd r t : 95.3k 1% r ccref : 301k, 0.1%, 25ppm/c, susumu rg1608p-3013-b-t5 r snsi : 3m, vishay wsk06123l000fea (10.7a input current limit) r snsb : 3m, vishay wsk06123l000fea r ntcbias : 10k 1% r ntc : vishay ntcs0402e3103flt l1: 10h, coil craft xal1010_103me or wrth elektronik 7443321000 m1, m2: fairchild fdmc8030 (dual) m3: fairchild fdmc8327l m4: vishay si7611dn d1: diodes inc 1n4448hlp c1: 120f 40v, 40hvh120m 10f 10f r ntc battery pack t 100pf 200 220nf sgnd ltc 4015 4015fb

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